1997-2018 Publications

• 2018
  • U. Farooq, H. Mehrez, M. Bhatti : “Inter-FPGA interconnect topologies exploration for multi-FPGA systems”, Design Automation for Embedded Systems, vol. 22 (1-2), pp. 117-140, (Springer Verlag) (2018)
  • R. Chotin‑Avot, U. Farooq, M. Azeem, M. Ravoson, H. Mehrez : “Novel architectural space exploration environment for multi-FPGA based prototyping systems”, Microprocessors and Microsystems: Embedded Hardware Design, vol. 56, pp. 169-183, (Elsevier) (2018)
• 2016
  • M. Azeem, R. Chotin‑Avot, U. Farooq, M. Ravoson, H. Mehrez : “Multiple FPGAs based prototyping and debugging with complete design flow”, IDT 2016 - 11^th International Design & Test Symposium, Hammamet, Tunisia, pp. 171-176, (IEEE) (2016)
  • U. Farooq, R. Chotin‑Avot, M. Azeem, M. Ravoson, H. Mehrez : “Inter-FPGA Routing Environment for Performance Exploration of Multi-FPGA Systems”, Rapid System Prototyping (RSP), Pittsburgh, United States, pp. 1-6 (2016)
  • U. Farooq, R. Chotin‑Avot, M. Azeem, Z. Cherif, M. Ravoson, S. Khan, H. Mehrez : “Using Timing-Driven Inter-FPGA Routing for Multi-FPGA Prototyping Exploration”, Euromicro Conference on Digital System Design (DSD), Limassol, Cyprus, pp. 641-645, (IEEE) (2016)
  • S. Chtourou, Z. Marrakchi, E. Amouri, V. Pangracious, M. Abid, H. Mehrez : “Improvement of cluster-based Mesh FPGA architecture using novel hierarchical interconnect topology and long routing wires”, Microprocessors and Microsystems: Embedded Hardware Design, vol. 40, pp. 16-26, (Elsevier) (2016)
  • K. Moussa Ali Abdellatif, R. Chotin‑Avot, H. Mehrez : “AEGIS-Based Efficient Solution for Secure Reconfiguration of FPGAs”, Proceedings of the Third Workshop on Cryptography and Security in Computing Systems, Prague, Czechia, pp. 37-40, (ACM) (2016)
  • S. Chtourou, M. Abid, Z. Marrakchi, E. Amouri, H. Mehrez : “The effect of interconnect depopulation on FPGA performances in terms of power, area and delay”, HPCS 2016 - International Conference on High Performance Computing & Simulation, Innsbruck, Austria, pp. 104-111, (IEEE) (2016)
  • S. Chtourou, Z. Marrakchi, E. Amouri, V. Pangracious, H. Mehrez, M. Abid : “Exploration of Mesh-Based FPGA Architecture: Comparison of 2D and 3D Technologies in Terms of Power, Area and Performance”, PDP 2016 - 24^th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, Heraklion, Crete, Greece, pp. 635-642, (IEEE Computer Society) (2016)
  • K. Moussa Ali Abdellatif, R. Chotin‑Avot, H. Mehrez : “AES-GCM and AEGIS: Efficient and High Speed Hardware Implementations”, Journal of Signal Processing Systems, pp. 1-12, (Springer) (2016)
• 2015
  • M. Turki, Z. Marrakchi, H. Mehrez, M. Abid : “Signal multiplexing approach to improve inter-FPGA bandwidth of prototyping platform”, Design Automation for Embedded Systems, vol. 19 (3), pp. 223-242, (Springer Verlag) (2015)
  • S. Chtourou, Z. Marrakchi, V. Pangracious, E. Amouri, H. Mehrez, M. Abid : “Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization”, ARC 2015 - 11^th International Symposium on Applied Reconfigurable Computing, vol. 9040, Lecture Notes in Computer Science, Bochum, Germany, pp. 411-418, (Springer) (2015)
  • V. Pangracious, Z. Marrakchi, H. Mehrez : “Design and Optimization of a Horizontally Partitioned, High-Speed, 3D Tree-Based FPGA”, IEEE Micro, vol. 35 (6), pp. 48-59, (Institute of Electrical and Electronics Engineers) (2015)
  • N. Belhadj, N. Bahri, Z. Marrakchi, M. Ayed, N. Masmoudi, H. Mehrez : “H.264/AVC high definition intra coding implementation on multiprocessor system on chip technology architecture”, IET Computers & Digital Techniques, vol. 9 (5), pp. 259-267, (Institution of Engineering and Technology) (2015)
  • V. Pangracious, Z. Marrakchi, H. Mehrez : “Three-Dimensional Design Methodologies for Tree-based FPGA Architecture”, vol. 350, Lecture Notes in Electrical Engineering, (Springer), (ISBN: 978-3-319-19173-7) (2015)
• 2014
  • A. Blanchardon, R. Chotin‑Avot, H. Mehrez, E. Amouri : “Impact of defect tolerance techniques on the criticality of a SRAM-based Mesh of Cluster FPGA”, ReConFig 2014 - International Conference on ReConFigurable Computing and FPGAs, Cancun, Mexico, pp. 1-6, (IEEE) (2014)
  • A. Blanchardon, R. Chotin‑Avot, H. Mehrez, E. Amouri : “Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using hardware redundancy”, FPL 2014 - 24^th International Conference on Field Programmable Logic and Applications, Munich, Germany, pp. 1-4, (IEEE) (2014)
  • K. Moussa Ali Abdellatif, R. Chotin‑Avot, H. Mehrez : “Authenticated Encryption on FPGAs from the Static Part to the Reconfigurable Part”, Microprocessors and Microsystems: Embedded Hardware Design, vol. 38 (6), pp. 526-538, (Elsevier) (2014)
  • S.‑U. Rehman, A. Blanchardon, A. Ben Dhia, M. Benabdenbi, R. Chotin‑Avot, L. Naviner, L. Anghel, H. Mehrez, E. Amouri, Z. Marrakchi : “Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI'14), Tampa, FL, United States, pp. 553-558, (IEEE) (2014)
  • J. Chae, P. Mougeat, J.‑A. Francois, R. Chotin‑Avot, H. Mehrez : “A reference-based specification tool for creating reliable library development specifications”, 12^th International New Circuits and Systems Conference, NEWCAS 2014, Trois-Rivieres, QC, Canada, pp. 133-136, (IEEE) (2014)
  • K. Moussa Ali Abdellatif, R. Chotin‑Avot, H. Mehrez : “FPGA-Based High Performance AES-GCM Using Efficient Karatsuba Ofman Algorithm”, 10^th International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications, ARC 2014, vol. 8405, Lecture Notes in Computer Science, Vilamoura, Portugal, pp. 13-24, (Springer) (2014)
  • V. Pangracious, E. Amouri, Z. Marrakchi, H. Mehrez : “Architecture level optimization of 3-dimensional tree-based FPGA”, Microelectronics Journal, vol. 45 (4), pp. 355-366, (Elsevier) (2014)
  • N. Belhadj, Z. Marrakchi, M. Ben ayed, N. Masmoudi, H. Mehrez : “MPSoC Architecture for Macro Blocks Line Partitioning of H.264/AVC Encoder”, International Journal of Embedded and Real-Time Communication Systems, vol. 5 (2), pp. 43-60, (IGI Global) (2014)
  • J. Chae, P. Mougeat, J.‑A. Francois, R. Chotin‑Avot, H. Mehrez : “A formalism of the specifications for library development”, IEEE International System-on-Chip Conference, Erlangen, Germany, pp. 307-312, (IEEE) (2014)
  • Q. Tang, M. Tuna, H. Mehrez : “Future Inter-FPGA Communication Architecture for Multi-FPGA Based Prototyping”, ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '14, Monterey, CA, United States, pp. 251-251, (ACM) (2014)
  • K. Moussa Ali Abdellatif, R. Chotin‑Avot, Z. Marrakchi, H. Mehrez, Q. Tang : “Towards high performance GHASH for pipelined AES-GCM using FPGAs”, ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '14, Monterey, CA, United States, pp. 242-242, (ACM) (2014)
  • S. Chtourou, M. Abid, V. Pangracious, E. Amouri, Z. Marrakchi, H. Mehrez : “Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation”, 3DIC 2014 - 2014 International 3D Systems Integration Conference, Kinsdale, Ireland, pp. 1-7, (IEEE) (2014)
  • E. Amouri, Sh. Bhasin, Y. Mathieu, T. Graba, J.‑L. Danger, H. Mehrez : “Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security”, FPL 2014 - 24^th International Conference on Field Programmable Logic and Applications, Munich, Germany, pp. 1-4, (IEEE) (2014)
  • A. Obeid, S. Qasim, Mohammed S. BenSaleh, Z. Marrakchi, H. Mehrez, H. Ghariani, M. Abid : “Flexible reconfigurable architecture for DSP applications”, SOCC 2014 - 27^th IEEE International System-on-Chip Conference, Las Vegas, NV, United States, pp. 204-209, (IEEE) (2014)
  • V. Pangracious, M. Marrakchi, H. Mehrez, Z. Marrakchi : “On wiring delays reduction of tree-based FPGA using 3-D fabric”, SOCC 2014 - 27^th IEEE International System-on-Chip Conference, Las Vegas, NV, United States, pp. 64-69, (IEEE) (2014)
  • Q. Tang, M. Tuna, H. Mehrez : “Multi-FPGA Prototyping Board Issue : the FPGA I/O Bottleneck”, Proceedings of International Conference on Embedded Computer Systems : Architectures, Modeling, and Simulation, Agios Konstantinos, Greece, pp. 207-214 (2014)
  • A. Kilic, D. Haghighitalab, H. Mehrez, H. Aboushady : “Low-power comb decimation filter for RF Sigma-Delta ADCs”, ISCAS 2014 - IEEE International Symposium on Circuits and Systems, Melbourne, Victoria, Australia, pp. 1596-1599, (IEEE) (2014)
  • Q. Tang, M. Tuna, H. Mehrez : “Performance Comparison between Multi-FPGA Prototyping Platforms: Hardwired Off-the-Shelf, Cabling and Custom”, Proceedings of International Symposium on Field-Programmable Custom Computing Machines, Boston, MA, United States, pp. 125-132, (IEEE) (2014)
  • V. Pangracious, Z. Marrakchi, N. Beltaief, H. Mehrez, U. Farooq : “Exploration and optimization of heterogeneous interconnect fabric of 3D tree-based FPGA”, DTIS 2014 - 9^th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, Santorini, Greece, pp. 1-6, (IEEE) (2014)
  • S. Chtourou, M. Abid, Z. Marrakchi, H. Mehrez : “Power consumption analysis for mesh based FPGA”, DTIS 2014 - 9^th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, Santorini, Greece, pp. 1-5, (IEEE) (2014)
  • A. Kilic, Z. Marrakchi, H. Mehrez : “A Top-Down Optimization Methodology for Mutually Exclusive Applications”, International Journal of Reconfigurable Computing, vol. 2014, pp. 827613:1-827613:18, (Hindawi Publishing Corporation) (2014)
  • K. Moussa Ali Abdellatif, R. Chotin‑Avot, H. Mehrez : “Low cost Solutions for Secure Remote Reconfiguration of FPGAs”, International Journal of Embedded Systems, vol. 6 (2-3), pp. 257-265, (Inderscience) (2014)
  • B. Ouattara, L. Doyen, D. Ney, H. Mehrez, P. Bazargan‑Sabet : “Power grid redundant path contribution in system on chip (SoC) robustness against electromigration”, Microelectronics Reliability, vol. 54 (9-10), pp. 1702-1706, (Elsevier) (2014)
• 2013
  • J. Chae, S. Bertrand, P.‑F. Ollagnon, P. Mougeat, J.‑A. Francois, R. Chotin‑Avot, H. Mehrez : “Efficient State-Dependent Power Model for Multi-bit Flip-Flop Banks”, IEEE International Midwest Symposium on Circuits and Systems, Columbus, United States, pp. 461-464, (IEEE) (2013)
  • K. Moussa Ali Abdellatif, R. Chotin‑Avot, H. Mehrez : “Improved Method for Parallel AES-GCM Cores Using FPGAs”, ReConFig 2013 - International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, pp. 1-4, (IEEE) (2013)
  • K. Moussa Ali Abdellatif, R. Chotin‑Avot, H. Mehrez : “Lightweight and Compact Solutions for Secure Reconfiguration of FPGAs”, International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, pp. 1-4, (IEEE) (2013)
  • Q. Tang, M. Tuna, H. Mehrez : “Routing algorithm for multi-FPGA based systems using multi-point physical tracks”, RSP 2013 - 24^th IEEE International Symposium on Rapid System Prototyping, Montreal, Canada, pp. 2-8, (IEEE) (2013)
  • V. Pangracious, H. Mehrez, Z. Marrakchi : “Designing a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technology”, IEEE International 3D Systems Integration Conference (3DIC), 2013, San Francisco, CA, United States, pp. 1-8, (IEEE) (2013)
  • V. Pangracious, H. Mehrez, U. Farooq, Z. Marrakchi : “High Performance 3-Dimensional Heterogeneous Tree-based FPGA Architectures (HT-FPGA)”, FPGAworld'13 - The 10^th FPGAworld Conference, Stockholm, Sweden, pp. 3:1-3:6, (ACM) (2013)
  • A. Ben Dhia, S. N. Pagliarini, L. Naviner, H. Mehrez, Ph. Matherat : “A defect-tolerant area-efficient multiplexer for basic blocks in SRAM-based FPGAs”, Microelectronics Reliability, vol. 53 (9-11), pp. 1189-1193, (Elsevier) (2013)
  • V. Pangracious, H. Mehrez, Z. Marrakchi : “Designing 3D tree-based FPGA: Interconnect Optimization and Thermal Analysis”, NEWCAS'13 - IEEE 11^th International Conference on New Circuits and Systems, Paris, France, pp. 1-4, (IEEE) (2013)
  • B. Ouattara, L. Doyen, D. Ney, H. Mehrez, P. Bazargan‑Sabet, F. Bana : “Redundancy Method to assess Electromigration Lifetime in power grid design”, IEEE International Interconnect Technology Conference (IITC),, Kyoto, Japan, pp. 81-83, (IEEE) (2013)
  • V. Pangracious, E. Amouri, H. Mehrez, Z. Marrakchi : “Physical Design Exploration of 3D Tree-based FPGA Architecture”, GLSVLSI'13 - The 23^rd ACM international conference on Great lakes symposium on VLSI, Paris, France, pp. 335-336, (ACM) (2013)
  • V. Pangracious, H. Mehrez, Z. Marrakchi : “Architecture Level TSV Count Minimization Methodology for 3D Tree-based FPGA”, Cool Chips XVI, Yokohama, Japan, pp. 1-3, (IEEE) (2013)
  • Q. Tang, M. Tuna, Z. Marrakchi, H. Mehrez : “Automatic Design Flow for Creating a Custom Multi-FPGA Board Netlist”, Proceedings of the 9^th International Symposium on Applied Reconfigurable Computing, ARC 2013, vol. 7806, Lecture Notes in Computer Science, Los Angeles, United States, pp. 221, (Springer) (2013)
  • S. Belloeil, R. Chotin‑Avot, H. Mehrez : “Exploring redundant arithmetics in computer-aided design of arithmetic datapaths”, Integration, the VLSI Journal, vol. 46 (2), pp. 104-118, (Elsevier) (2013)
  • V. Pangracious, Z. Marrakchi, E. Amouri, H. Mehrez : “Performance analysis and optimization of high density tree-based 3d multilevel FPGA”, Reconfigurable Computing: Architectures, Tools and Applications, vol. 7806, Lecture Notes in Computer Science, Los Angeles, CA, United States, pp. 197-209, (Springer) (2013)
  • E. Amouri, A. Blanchardon, R. Chotin‑Avot, H. Mehrez, Z. Marrakchi : “Efficient Multilevel Interconnect Topology for Cluster-based Mesh FPGA Architecture”, ReConFig 2013 - International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, pp. 1-6, (IEEE) (2013)
  • A. Ben Dhia, S. Ur Rehman, A. Blanchardon, L. Naviner, M. Benabdenbi, R. Chotin‑Avot, H. Mehrez, E. Amouri, Z. Marrakchi : “A Defect-tolerant Cluster in a Mesh SRAM-based FPGA”, International Conference on Field-Programmable Technology (FPT), Kyoto, Japan, pp. 434-437, (IEEE Computer Society) (2013)
  • V. Pangracious, Z. Marrakchi, H. Mehrez : “Design and optimization of heterogeneous tree-based FPGA using 3D technology”, FPT 2013 - International Conference on Field-Programmable Technology, Kyoto, Japan, pp. 334-337, (IEEE) (2013)
  • V. Pangracious, H. Mehrez, N. Beltaief, Z. Marrakchi, U. Farooq : “Exploration environment for 3D heterogeneous tree-based FPGA architectures (3D HT-FPGA)”, ReConFig 2013 - International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, pp. 1-6, (IEEE) (2013)
  • K. Moussa Ali Abdellatif, R. Chotin‑Avot, H. Mehrez : “High Speed Authenticated Encryption for Slow Changing Key Applications Using Reconfigurable Devices”, Wireless Days (WD), 2013 IFIP, Valencia, Spain, pp. 1-6 (2013)
  • M. Turki, H. Mehrez, Z. Marrakchi, M. Abid : “Partitioning constraints and signal routing approach for multi-FPGA prototyping platform”, ISSoC 2013 - International Symposium on System on Chip, Tampere, Finland, pp. 1-4, (IEEE) (2013)
  • K. Moussa Ali Abdellatif, R. Chotin‑Avot, H. Mehrez : “Protecting FPGA Bitstreams Using Authenticated Encryption”, 11^th IEEE International Conference of New Circuits and Systems (NEWCAS), Paris, France, pp. 1-4, (IEEE) (2013)
  • V. Pangracious, H. Mehrez, Z. Marrakchi : “TSV count minimization and thermal analysis for 3D Tree-based FPGA”, ICICDT 2013 - International Conference on IC Design & Technology, Pavia, Italy, pp. 223-226, (IEEE) (2013)
  • M. Turki, Z. Marrakchi, H. Mehrez, M. Abid : “Iterative Routing Algorithm of Inter-FPGA Signals for Multi-FPGA Prototyping Platform”, ARC 2013 - 9^th International Symposium on Reconfigurable Computing: Architectures, Tools and Applications, vol. 7806, Lecture Notes in Computer Science, Los Angeles, CA, United States, pp. 210-217, (Springer) (2013)
  • N. Belhadj, N. Bahri, M. Ali Ben Ayed, Z. Marrakchi, H. Mehrez : “Data level parallelism for H264/AVC baseline intra-prediction chain on MPSoC”, 2013 10^th International Multi-Conference on Systems, Signals & Devices (SSD), Hammamet, Tunisia, (IEEE) (2013)
  • J. Chae, P. Mougeat, J.‑A. Francois, R. Chotin‑Avot, H. Mehrez : “Formalisme de la spécification de la plateforme de conception pour le développement de la bibliothèque”, Journees Nationales du Reseau Doctoral de Micro-electronique, Grenoble, France, pp. 1-4 (2013)
  • U. Farooq, H. Parvez, H. Mehrez, Z. Marrakchi : “Exploration and optimization of a homogeneous tree-based application specific inflexible FPGA”, Microelectronics Journal, vol. 44 (12), pp. 1052-1062, (Elsevier) (2013)
  • M. Turki, Z. Marrakchi, H. Mehrez, M. Abid : “Frequency Optimization Objective during System Prototyping on Multi-FPGA Platform”, International Journal of Reconfigurable Computing, vol. 2013, pp. 853510, (Hindawi Publishing Corporation) (2013)
  • E. Amouri, H. Mehrez, Z. Marrakchi : “Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA”, International Journal of Reconfigurable Computing, vol. 2013 (802436), pp. 24, (Hindawi Publishing Corporation) (2013)
• 2012
  • K. Moussa Ali Abdellatif, R. Chotin‑Avot, H. Mehrez : “Efficient Parallel-Pipelined GHASH for Message Authentication”, International Conference on Reconfigurable Computing and FPGAs (ReConFig 2012), Cancun, Mexico, pp. 1-6 (2012)
  • M. Turki, H. Mehrez, Z. Marrakchi : “Multi-FPGA Prototyping Environment: Large Benchmark Generation and Signals Routing”, 2014 International Conference on Reconfigurable computing and FPGA, Cancun, Mexico (2012)
  • U. Farooq, H. Parvez, Z. Marrakchi, H. Mehrez : “A New Heterogeneous Tree-based Application Specific FPGA and Its Comparison with Mesh-based Application Specific FPGA”, Microprocessors and Microsystems: Embedded Hardware Design, vol. 36 (8), pp. 588-605, (Elsevier) (2012)
  • Q. Tang, M. Tuna, H. Mehrez : “Design for prototyping of a parameterizable cluster-based Multi-Core System-on-Chip on a multi-FPGA board”, Proceedings of the 23^rd IEEE International Symposium on Rapid System Prototyping, Tampere, Finland, pp. 71-77 (2012)
  • K. Moussa Ali Abdellatif, R. Chotin‑Avot, H. Mehrez : “The Effect of S-box Design on Pipelined AES Using FPGAs”, Colloque GDR SOC-SIP, Paris, France, pp. 1-4 (2012)
  • F. Hamzaoui, R. Chotin‑Avot, P. Renault, H. Mehrez, H. Belmabrouk, M. Machhout : “Synthesis and Optimization of Quantum Boolean Circuit Using the Truth Table Method”, International Workshop on Number Theory, Codes, Cryptography and Communication Systems (NTCCCS), Oujda, Morocco, pp. 192-197 (2012)
  • A. Blanchardon, R. Chotin‑Avot, H. Mehrez : “Générateur d’Architecture de FPGA”, Colloque GDR SOC-SIP, Paris, France, pp. 1-3 (2012)
  • A. Kilic, Z. Marrakchi, M. Tuna, H. Mehrez : “A Logic Sharing Synthesis Tool for Mutually Exclusive Applications”, Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2012 7^th International Conference on, Gammarth, Tunisia, pp. 1-6 (2012)
  • U. Farooq, Z. Marrakchi, H. Mehrez : “Tree Based Heterogeneous FPGA Architectures, Application Specific Exploration and Optimization”, (Springer), (ISBN: 978-1-4614-3593-8) (2012)
• 2011
  • Z. Guitouni, R. Chotin‑Avot, M. Machhout, H. Mehrez, R. Tourki : “High Performances ASIC Based Elliptic Curve Cryptographic Processor over GF(2m)”, International Journal of Computer Applications, vol. Special Issue on Network Security and Cryptography (NSC) (4), pp. 1-10, (Foundation of Computer Science) (2011)
  • H. Parvez, Z. Marrakchi, A. Kilic, H. Mehrez : “Application-Specific FPGA using heterogeneous logic blocks”, ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 4 (3), pp. 1-24, (ACM) (2011)
  • E. Amouri, Z. Marrakchi, H. Mehrez : “Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA”, 6^th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2011, Montpellier, France, pp. 1-4, (IEEE) (2011)
  • F. Hamzaoui, R. Chotin‑Avot, M. Machhout, H. Mehrez, H. Belmabrouk : “Quantum circuits design and simulation”, The First International Conference on "Research to Applications & Markets" (RAM 2011), Monastir, Tunisia, pp. 115-115 (2011)
  • U. Farooq, H. Parvez, E. Amouri, H. Mehrez, Z. Marrakchi : “Exploring the Effect of LUT and Arity Size on a Tree-based Application Specific Inflexible FPGA”, International conference on Design & Technology of Integrated Systems (DTIS), Athens, Greece, pp. 1-6, (IEEE) (2011)
  • U. Farooq, H. Parvez, Z. Marrakchi, H. Mehrez : “Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGA”, The 7^th International Symposium on Applied Reconfigurable Computing, vol. 6578, Lecture Notes in Computer Science, Belfast, United Kingdom, pp. 218-229, (Springer) (2011)
  • S. Belloeil, R. Chotin‑Avot, H. Mehrez : “Stratus: Free design of highly parametrized VLSI modules interoperable with commercial tools”, ISQED 2011 - 12^th International Symposium on Quality Electronic Design, Santa Clara, CA, United States, pp. 502-507, (IEEE) (2011)
  • H. Parvez, H. Mehrez : “Application-Specific Mesh-based Heterogeneous FPGA Architectures”, vol. 202, (Springer), (ISBN: 978-1-4419-7927-8) (2011)
  • U. Farooq, H. Parvez, H. Mehrez, Z. Marrakchi : “Exploration of Heterogeneous FPGA Arcrchitectures”, International Journal of Reconfigurable Computing, vol. 2011, pp. 121404, (Hindawi Publishing Corporation) (2011)
• 2010
  • U. Farooq, Z. Marrakchi, H. Mehrez : “A New Datapath-Oriented Tree-based FPGA Architecture”, IEEE International Conference on Microelectronics (ICM), Cairo, Egypt, pp. 403-406, (IEEE) (2010)
  • F. Hamzaoui, B. Othmani, R. Chotin‑Avot, M. Machhout, H. Belmabrouk, H. Mehrez : “Modélisation et simplification de circuits quantiques”, Materiaux 2010, Mahdia, Tunisia, pp. 2-2 (2010)
  • H. Parvez, Z. Marrakchi, H. Mehrez : “Application Specific FPGA Using Heterogeneous Logic Blocks”, ARC International Symposium on Applied Reconfigurable Computing, Bangkok, Thailand, pp. 92-109, (Springer) (2010)
  • H. Parvez, Z. Marrakchi, H. Mehrez : “Heterogeneous-ASIF: An Application Specific Inflexible FPGA using Heterogeneous logic blocks”, FPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, California, United States, pp. 290-290, (ACM) (2010)
  • M. Turki, M. Abid, Z. Marrakchi, H. Mehrez : “Routability driven placement for mesh-based FPGA architecture”, IDT 2010 - 5^th International Design and Test Workshop, Abu Dhabi, United Arab Emirates, pp. 85-90, (IEEE) (2010)
  • L. Noury, H. Mehrez : “A flexible realtime system for broadband time-frequency analysis in 130 NM CMOS”, ICECS 2010 - 17^th IEEE International Conference on Electronics, Circuits and Systems, Athens, Greece, pp. 251-254, (IEEE) (2010)
  • E. Amouri, Z. Marrakchi, H. Mehrez : “Controlled placement and routing techniques to improve timing balance of WDDL designs in Mesh-based FPGA”, APCCAS 2010 - IEEE Asia Pacific Conference on Circuits and Systems, Kuala Lumpur, Malaysia, pp. 296-299, (IEEE) (2010)
  • Z. Marrakchi, H. Parvez, A. Kilic, H. Mehrez, H. Marrakchi : “On the optimization of FPGA area depending on target applications”, APCCAS 2010 - IEEE Asia Pacific Conference on Circuits and Systems, Kuala Lumpur, Malaysia, pp. 308-311, (IEEE) (2010)
  • Z. Guitouni, R. Chotin‑Avot, M. Machhout, H. Mehrez, R. Tourki : “Design and FPGA Implementation of Modular Multiplication Methods Using Cellular Automata”, DTIS IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology, Hammamet, Tunisia, pp. 1-5, (IEEE) (2010)
• 2009
  • H. Parvez, Z. Marrakchi, H. Mehrez : “ASIF: Application Specific Inflexible FPGA”, ICFPT International Conference on Field-Programmable Technology, Sydney, Australia, pp. 112-119, (IEEE) (2009)
  • Z. Marrakchi, U. Farooq, H. Mrabet, H. Mehrez : “Comparison of Tree-Based and Mesh-Based Coarse-Grained FPGA Architectures”, ICM International Conference on Microelectronics, Marrakech, Morocco, pp. 248-251, (IEEE) (2009)
  • E. Amouri, H. Mrabet, Z. Marrakchi, H. Mehrez : “Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing”, ReConFig International Conference on Reconfigurable Computing and FPGAs 2009, Cancun, Mexico, pp. 201-206, (IEEE) (2009)
  • E. Amouri, H. Mrabet, Z. Marrakchi, H. Mehrez : “Placement and Routing Techniques to Improve Delay Balance of WDDL Netlist in MFPGA”, IEEE International Conference on Electronics, Circuits, and Systems - ICECS 2009, Hammamet, Tunisia, pp. 791-794, (IEEE) (2009)
  • U. Farooq, H. Parvez, Z. Marrakchi, H. Mehrez : “A New Tree-based coarse-grained FPGA Architecture”, IEEE International Conference on PhD. Research in MicroElectronics, PRIME'09, Cork, Ireland, pp. 48-51, (IEEE) (2009)
  • Z. Marrakchi, H. Mrabet, H. Mehrez : “FPGA Interconnect Topologies Exploration”, International Journal of Reconfigurable Computing, vol. 2009, pp. 259837, (Hindawi Publishing Corporation) (2009)
• 2008
  • H. Parvez, Z. Marrakchi, U. Farooq, H. Mehrez : “A New Coarse-grained FPGA Architecture Exploration Environment”, ICFPT International Conference on Field-Programmable Technology, Taipei, Taiwan, Province of China, pp. 285-288, (IEEE) (2008)
  • H. Mrabet, H. Parvez, Z. Marrakchi, H. Mehrez : “Automatic Layout Generator of Domain Specific FPGA:”, ICM International Conference on Microelectronics, Sharjah, United Arab Emirates, pp. 183-186, (IEEE) (2008)
  • H. Parvez, Z. Marrakchi, H. Mehrez : “Enhanced Methodology and Tools for Exploring Domain-Specific Coarse-grained FPGAs”, ReConFig International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, pp. 121-126, (IEEE) (2008)
  • U. Farooq, Z. Marrakchi, H. Mrabet, H. Mehrez : “The Effect of LUT and Cluster Size on a Tree based FPGA Architecture”, ReConFig International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, pp. 115-120, (IEEE) (2008)
  • H. Parvez, H. Mrabet, H. Mehrez : “Generic Techniques and CAD tools for automated generation of FPGA Layout”, PRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics, Istanbul, Türkiye, pp. 141-144, (IEEE) (2008)
  • Z. Marrakchi, H. Mrabet, E. Amouri, H. Mehrez : “Efficient Tree Topology for FPGA Interconnect Network”, GLSVLSI ACM Great Lakes Symposium on VLSI, Orlando, Florida, United States, pp. 321-326, (ACM) (2008)
  • S. Belloeil, R. Chotin‑Avot, H. Mehrez, A. Munier‑Kordon : “Automatic Allocation of Redundant Operators in Arithmetic Data path Optimization”, DASIP IEEE International Conference on Design and Architectures for Signal and Image Processing, Bruxelles, Belgium, pp. 176-183 (2008)
  • S. Belloeil, R. Chotin‑Avot, H. Mehrez : “Arithmetic Data path Optimization using Borrow-Save Representation”, ISVLSI IEEE Computer Society Annual Symposium on Emerging VLSI, Montpellier, France, pp. 4-9, (IEEE) (2008)
  • A. Abril Garcia, H. Mehrez, F. Pétrot, J. Gobert, C. Miro : “Estimation et optimisation de la consommation dans les SoC utilisant la simulation précise au cycle”, Revue des Sciences et Technologies de l'Information - Série TSI : Technique et Science Informatiques, vol. 27 (1-2), pp. 203-233, (Lavoisier) (2008)
  • Z. Marrakchi, H. Mrabet, Ch. Masson, H. Mehrez : “Performances Comparison between Multilevel Hierarchical and Mesh FPGA Interconnects”, International Journal of Electronics, vol. 95 (3), pp. 275-289, (Taylor & Francis) (2008)
• 2007
  • Z. Marrakchi, H. Mrabet, Ch. Masson, H. Mehrez : “Efficient Mesh of Tree Interconnect for FPGA Architecture”, ICFPT International Conference on Field-Programmable Technology, Kitakyushu, Japan, pp. 269-272, (IEEE) (2007)
  • S. Belloeil, D. Dupuis, Ch. Masson, J.‑P. Chaput, H. Mehrez : “Stratus: A procedural circuit description language based upon Python”, ICM International Conference on Microelectronics, Cairo, Egypt, pp. 275-278, (IEEE) (2007)
  • S. Belloeil, R. Chotin‑Avot, H. Mehrez : “Data Path Optimization using Redundant Arithmetic and Pattern Matching”, Workshop on Design and Architectures for Signal and Image Processing (DASIP'2007), Grenoble, France, pp. 281-288 (2007)
  • L. Noury, H. Mehrez, F. Durbin, A. Tissot : “A Cascadable ASIC Prototype for Real Time Time-Frequency Analysis”, MWSCAS Midwest Symposium on Circuits and Systems, Montreal, Canada, pp. 690-693, (IEEE) (2007)
  • L. Noury, F. Durbin, H. Mehrez, A. Tissot : “A Generic ASIC Architecture for Real Time Time-Frequency Analysis of Non-stationary Large Bandwidth Signals”, IMTC IEEE Instrumentation and Measurement Technology Conference, Warsaw, Poland, pp. 1-5, (IEEE) (2007)
  • Z. Marrakchi, H. Mrabet, Ch. Masson, H. Mehrez : “Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances”, NoC ACM/IEEE International Symposium on Networks-on-Chip, Princeton, United States, pp. 243-252, (IEEE) (2007)
  • Z. Marrakchi, H. Mrabet, G. Souffleteau, Ch. Masson, H. Mehrez : “A Routability Driven Partitioning and Detailed Placement Approach for Multilevel Hierarchical FPGA”, FPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, Californie, United States, pp. 225-225 (2007)
• 2006
  • H. Mrabet, Z. Marrakchi, P. Souillot, H. Mehrez : “Performances Improvement of FPGA using Novel Multilevel Hierarchical Interconnection Structure”, ICCAD IEEE/ACM International Conference on Computer-Aided Design, San Jose, California, United States, pp. 675-679, (IEEE) (2006)
  • H. Mrabet, Z. Marrakchi, H. Mehrez, A. Tissot : “Implementation of Scalable Embedded FPGA for SOC”, DTIS IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology, Tunis, Tunisia, pp. 74-77, (IEEE) (2006)
  • Z. Marrakchi, H. Mrabet, H. Mehrez : “Performances comparison between Multilevel hierarchical and Mesh FPGA”, DTIS IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology, Tunis, Tunisia, pp. 166-171, (IEEE) (2006)
  • Z. Marrakchi, H. Mrabet, H. Mehrez : “Evaluation of Hierarchical FPGA partitioning methodologies based on architecture Rent Parameter”, PRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics, Otranto, Italy, pp. 85-88, (IEEE) (2006)
  • Z. Marrakchi, H. Mrabet, H. Mehrez : “A new Multilevel Hierarchical MFPGA and its suitable configuration tools”, ISVLSI IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, Karlsruhe, Germany, pp. 263-268, (IEEE) (2006)
  • H. Mrabet, Z. Marrakchi, P. Souillot, H. Mehrez : “A multilevel hierarchical interconnection structure for FPGA”, FPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, California, United States, pp. 225-225, (ACM) (2006)
  • Z. Marrakchi, H. Mrabet, H. Mehrez : “Configuration tools for a new multilevel hierarchical FPGA”, FPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, California, United States, pp. 229-229, (ACM) (2006)
  • H. Mrabet, Z. Marrakchi, P. Souillot, H. Mehrez, A. Tissot : “Performance Improvement of FPGA Using Novel Multilevel Hierarchical Interconnection Structure”, ReCoSoC 2006 - 2^nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, Montpellier, France, pp. 117-123, (Univ. Montpellier II) (2006)
  • S. Belloeil, J.‑P. Chaput, R. Chotin‑Avot, Ch. Masson, H. Mehrez : “Stratus : Un environnement de développement de circuits”, JP CNFM Journées pédagogiques du CNFM, Saint-Malo, France, pp. 57-61 (2006)
• 2005
  • Z. Marrakchi, H. Mrabet, H. Mehrez : “Hierarchical FPGA clustering to improve routability”, PRIME 2005 - IEEE Conference on Ph.D. Research in MicroElectronics and Electronics, vol. 1, Lausanne, Switzerland, pp. 165-168, (IEEE) (2005)
  • H. Mrabet, Z. Marrakchi, H. Mehrez, A. Tissot : “Implementation of Scalable Embedded FPGA for SOC”, ReCoSoC 2005 - 1^st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, Montpellier, France, pp. 74-77 (2005)
  • A. Abril Garcia, H. Mehrez, F. Pétrot, J. Gobert, C. Miro : “Energy Estimation and Optimisation of Embedded Systems using Cycle Accurate Simulation”, FTFC 2005 - 5^es Journées d'études Faible Tension Faible Consommation, Paris, France, pp. 29-32 (2005)
  • S. Belloeil, H. Mehrez : “Optimisation de chemins de données par l’utilisation de l’arithmétique redondante”, JNRDM 2005 - 8^es Journées Nationales du Réseau Doctoral en Microélectronique, Paris, France, pp. 268-270 (2005)
  • Z. Marrakchi, H. Mrabet, H. Mehrez : “Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation”, ReConFig 2005 - International Conference on Reconfigurable Computing and FPGAs, Puebla City, Mexico, pp. 21-25, (IEEE Computer Society) (2005)
  • A. Abril Garcia, H. Mehrez, F. Pétrot, J. Gobert, C. Miro : “Energy estimation and optimization in architectural descriptions of complex embedded systems”, Microtechnologies for the New Millennium 2005 : VLSI Circuits and Systems, vol. 5837, SPIE Proceedings, Sevilla, Spain, pp. 456-466, (SPIE) (2005)
  • A. Abril Garcia, H. Mehrez, F. Pétrot, J. Gobert, C. Miro : “A High Level SoC Energy Analysis Method with Good Accuracy Using Cycle Accurate Simulation”, IEEE Symposium on low power and high-speed chips (COOL Chips VIII), Yokohama, Japan, pp. 195, (IEEE) (2005)
• 2004
  • L. Noury, H. Mehrez, F. Durbin, A. Tissot : “Use of multiple numeration systems for architecture and design of a high performance FIR filter netlist generator”, ICM 2004 - 16^th International Conference on Microelectronics, Tunis, Tunisia, pp. 547-550, (IEEE) (2004)
  • R. Chotin‑Avot, H. Mehrez : “Hardware implementation of discrete stochastic arithmetic”, Numerical Algorithms, vol. 37 (1-4), pp. 21-33, (Springer Verlag) (2004)
  • H. Mrabet, Z. Marrakchi, H. Mehrez, A. Tissot : “Automatic Layout of Scalable Embedded Field Programmable Gate Array”, ICEEC 2004 - International Conference on Electrical Electronic and Computer Engineering, Cairo, Egypt, pp. 469-472, (IEEE) (2004)
  • L. Noury, H. Mehrez : “Générateur de netlist de filtres numériques RIF optimisés”, JNRDM 2004 - 7^es Journées Nationales du Réseau Doctoral en Microélectronique, Marseille, France, pp. 451-453 (2004)
• 2003
  • R. Chotin‑Avot, H. Mehrez : “Hardware implementation of discrete stochastic arithmetic”, 6^th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'03), Poznan, Poland, pp. 57-64 (2003)
• 2002
  • R. Chotin, H. Mehrez : “A Floating-Point Unit using stochastic arithmetic compliant with the IEEE-754 standard”, 9^th IEEE International Conference on Electronics Circuits and Systems (ICECS'2002), Dubrovnik, Croatia, pp. 603-606 (2002)
  • R. Chotin, H. Mehrez : “Hardware implementation of the CESTAC method”, 10^th GAMM - IMACS International Symposium on Scientific Computing Computer Arithmetic and Validated Numerics (SCAN'2002), Paris, France, pp. 162-162 (2002)
  • R. Chotin, H. Mehrez : “Hardware implementation of a method to control round-off errors”, 6^th WSEAS International Multiconference on Circuits Systems Communications and Computers (CSCC'2002), Rethymnon, Greece, pp. 157-162 (2002)
  • G.‑B. Abril, J. Gobert, Th. Dombek, H. Mehrez, F. Pétrot : “Energy Estimations in High Level Cycle-Accurate Descriptions of Embedded Systems”, The 5^th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'2002), Brno, Czechia, pp. 228-235 (2002)
  • R. Chotin, H. Mehrez : “Implantation matérielle d’une méthode de contrôle des erreurs d’arrondi de calcul”, Troisième colloque du GDR CAO de circuits et systèmes intégrés, Paris, France, pp. 63-66 (2002)
  • R. Chotin, H. Mehrez : “Une unité de calcul flottant utilisant l’arithmétique stochastique”, Vèmes Journées Nationales du Réseau Doctoral de Micro-électronique (JNRDM'2002), Grenoble, France, pp. 217-218 (2002)
• 2001
  • Y. Bajot, H. Mehrez : “Les systèmes de traitement numérique du signal”, (2001)
  • H. Aboushady, Y. Dumonteix, M.‑M. Louërat, H. Mehrez : “Efficient Polyphase decomposition of Comb decimation filters in sigma-delta analog-to-digital converters”, IEEE Transactions on Circuits and Systems Part 2 Analog and Digital Signal Processing, vol. 48 (10), pp. 898-903, (Institute of Electrical and Electronics Engineers (IEEE)) (2001)
  • Y. Dumonteix, Y. Bajot, H. Mehrez : “A fast and low-power distance computation unit dedicated to neural networks, based on redundant arithmetic”, IEEE International Symposium on Circuits and Systems (ISCAS'2001), vol. 4, Sydney, Australia, pp. 878-881, (IEEE) (2001)
• 2000
  • Y. Bajot, H. Mehrez : “GSM EFR Vocoder on a Configurable DSP Core, A Quantitative Analysis”, International Conference On Signal Processing Applications and Technologies (ICSPAT 2000), Dallas, Texas, United States, pp. 1-6 (2000)
  • Y. Dumonteix, H. Aboushady, H. Mehrez, M.‑M. Rosset‑Louërat : “Low-power Comb Decimation Filter Using Polyphase Decomposition For Mono-bit Sigma-Delta Analog-to-Digital Converters”, International Conference On Signal Processing Applications and Technologies (ICSPAT 2000), vol. 1, Dallas, Texas, United States, pp. 432-435 (2000)
  • H. Aboushady, Y. Dumonteix, M.‑M. Rosset‑Louërat, H. Mehrez : “Efficient Polyphase Decomposition of Comb Decimation Filters in Sigma-Delta Analog-to-Digital Converters”, 43^rd IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2000), Lansing, MI, United States, pp. 432-435, (IEEE) (2000)
  • Y. Dumonteix, H. Mehrez : “A family of redundant multipliers dedicated to fast computation for signal processing”, IEEE International Symposium on Circuits and Systems (ISCAS 2000), vol. 5, Geneva, Switzerland, pp. 325-328, (IEEE) (2000)
  • M. Aberbour, H. Mehrez, F. Durbin, J. Haussy, P. Lalande, A. Tissot : “A System-On-A-Chip for Pattern Recognition Architecture and Design Methodology”, CAMP 2000 - Fifth International Workshop on Computer Architectures for Machine Perception, Padova, Italy, pp. 155-162, (IEEE Computer Society) (2000)
  • R. Chotin, Y. Dumonteix, H. Mehrez : “Use of Redundant Arithmetic on Architecture and Design of a High Performance DCT Macro-bloc Generator”, 15^th Design of Circuits and Integrated Systems Conference (DCIS), Montpellier, France, pp. 428-433 (2000)
• 1999
  • Y. Bajot, H. Mehrez : “A Macro-Block Based Methodology for ASIP Core Design”, International Conference On Signal Processing Applications and Technologies (ICSPAT'99), Orlando, FL, United States, pp. 302-305 (1999)
• 1998
  • M. Aberbour, H. Mehrez, F. Durbin, Th. Garié, A. Tissot : “System Level Design of a Pattern Recognition System Based on the Gabor Wavelets”, IEEE-SP Conference on Time-Frequency Time-Scale Analysis (TFTS'98), Pittsburgh, PA, United States, pp. 237-240, (IEEE) (1998)
  • M. Aberbour, H. Mehrez, F. Durbin, Th. Garié, A. Tissot : “Algorithms and VLSI Architectures for Pattern Recognition Based on the Gabor Wavelets”, International Conference on Signal Processing Applications and Technology (ICSPAT'98), Toronto, Canada, pp. 1455-1459 (1998)
  • M. Aberbour, H. Mehrez : “Architecture and design Methodology of the RBF-DDA Neural Network”, IEEE International Symposium on Circuits and Systems (ISCAS'98), vol. 3, Monterey, CA, United States, pp. 199-202, (IEEE) (1998)
  • M. Aberbour, A. Houelle, H. Mehrez, N. Vaucher, A. Guyot : “On portable macrocell FPU generators for division and square root operators complying to the full IEEE-754 standard”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 6 (1), pp. 114-121, (IEEE) (1998)
• 1997
  • A. Guyot, S.‑J. Abou‑Samra, M. Aberbour, A. Houelle, H. Mehrez, N. Vaucher : “Modelling and synthesis of optimal adders under left-to-right input arrival”, IFIP International Workshop on Logic and Architecture Synthesis (IWLAS'97), Grenoble, France, (IFIP) (1997)
  • M. Aberbour, F. Ahmad, H. Mehrez : “A Hardware Implementation of an RBF Neural Network : Architecture and Design Methodology”, International Conference on Signal Processing and Technology 97, vol. 3, San Diego, CA, United States, pp. 199-202 (1997)
  • M. Aberbour, A. Houelle, H. Mehrez, N. Vaucher, A. Guyot : “A time driven adder generator architecture”, 9^th IFIP International Conference on Very Large Scale Integration (VLSI'97), Gramado, RS, Brazil, pp. 453-463, (Springer) (1997)
  • E. Rejouan, H. Mehrez : “Automatic Generation Of Self Testing ROM”, 4^th Mixed Design of Integrated Circuits and Systems (MIXDES'1997), Poznan, Poland, pp. 1-5 (1997)
  • M. Aberbour, A. Derieux, H. Mehrez, N. Vaucher : “Teaching the design of a chip under the Cadence Opus environment using the Alliance cell libraries”, MSE '97 - IEEE International Conference on Microelectronic Systems Education, Arlington, VA, United States, pp. 81-82, (IEEE Computer Society) (1997)