Electromigration (EMG) is a consequence of miniaturization of integrated circuits in general and the reduction of interconnect dimensions in particular. It is identified as one of the critical reliability phenomenon for integrated circuits designed in submicron technologies. The methods of checking this phenomenon at design level are mostly based on current density rules and temperature. These rules are becoming difficult to implement due to increasing current density in interconnection network. This thesis is based on researching for ways to improve detection of electromigration risks at design level. The goal is to establish a relation between electrical rules and interconnect degradation mechanism. Results obtained from ageing tests permit us to relax current limit without altered circuit lifetimes. Finally, this project has been instrumental to define design rules based on optimization of clock tree cells placement in integrated circuit power grid. The application of solution proposed during this work permit to design robust circuits toward EMG.