20 PhD graduated 2001 - 2021

1997-2022 Publications

• 2022
  • A. Pavlidis, E. Faehn, M.‑M. Louërat, Haralampos‑G. Stratigopoulos : “Run-Time Hardware Trojan Detection in Analog and Mixed-Signal ICs”, 40^th IEEE VLSI Test Symposium 2022, San Diego, United States, pp. 1-8, (IEEE) (2022)
  • M. Elshamy, G. Di Natale, A. Sayed, A. Pavlidis, M.‑M. Louërat, H. Aboushady, Haralampos‑G. Stratigopoulos : “Digital-to-Analog Hardware Trojan Attacks”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69 (2), pp. 573-586, (IEEE) (2022)
  • M. Tlili, A. Sayed, D. Mahmoud, M.‑M. Louërat, H. Aboushady, Haralampos‑G. Stratigopoulos : “Anti-Piracy of Analog and Mixed-Signal Circuits in FD-SOI”, 2022 27^th Asia and South Pacific Design Automation Conference (ASP-DAC), Virtual, Taiwan, Province of China, pp. 423-428, (IEEE) (2022)
• 2021
  • M. Elshamy, A. Sayed, M.‑M. Louërat, H. Aboushady, Haralampos‑G. Stratigopoulos : “Locking by Untuning: A Lock-Less Approach for Analog and Mixed-Signal IC Security”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29 (12), pp. 2130-2142, (IEEE) (2021)
  • A. Pavlidis, E. Faehn, M.‑M. Louërat, Haralampos‑G. Stratigopoulos : “BIST-Assisted Analog Fault Diagnosis”, 26^th IEEE European Test Symposium, Bruges (virtual), Belgium, pp. 1-6, (IEEE) (2021)
  • A. Pavlidis, M.‑M. Louërat, E. Faehn, A. Kumar, Haralampos‑G. Stratigopoulos : “SymBIST: Symmetry-Based Analog and Mixed-Signal Built-In Self-Test for Functional Safety”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68 (6), pp. 2580-2593, (IEEE) (2021)
  • J. Leonhard, M. Elshamy, M.‑M. Louërat, Haralampos‑G. Stratigopoulos : “Breaking Analog Biasing Locking Techniques via Re-Synthesis”, 26^th Asia and South Pacific Design Automation Conference (ASPDAC '21), Tokyo, Japan (2021)
• 2020
  • F. Pêcheux, L. Andrade Porras, M.‑M. Louërat, I. Bournias, R. Chotin, D. Genius : “Virtual Prototyping of Open Source Heterogeneous Systems with an Open Source Framework Featuring SystemC MDVP Extensions”, 2020 Forum for Specification and Design Languages (FDL), Kiel, Germany, pp. 1-8, (IEEE) (2020)
  • A. Sayed, T. Badran, M.‑M. Louërat, H. Aboushady : “A 1.5-to-3.0GHz Tunable RF Sigma-Delta ADC With a Fixed Set of Coefficients and a Programmable Loop Delay”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67 (9), pp. 1559-1563, (Institute of Electrical and Electronics Engineers) (2020)
  • M. Elshamy, G. Di Natale, A. Pavlidis, M.‑M. Louërat, Haralampos‑G. Stratigopoulos : “Hardware Trojan Attacks in Analog/Mixed-Signal ICs via the Test Access Mechanism”, 2020 IEEE European Test Symposium (ETS), Tallinn, Estonia (2020)
  • M. Terosiet, E. Zianbetov, F. Vallette, M.‑M. Louërat, P. Garda, D. Galayko, S. Feruglio : “A comprehensive in-depth study of tri-state inverter based DCO”, Microelectronics Journal, vol. 99, pp. 104760, (Elsevier) (2020)
  • M. Elshamy, A. Sayed, M.‑M. Louërat, A. Rhouni, H. Aboushady, Haralampos‑G. Stratigopoulos : “Securing Programmable Analog ICs Against Piracy”, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France (2020)
  • A. Pavlidis, M.‑M. Louërat, E. Faehn, A. Kumar, Haralampos‑G. Stratigopoulos : “Symmetry-based A/M-S BIST (SymBIST): Demonstration on a SAR ADC IP”, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France (2020)
  • J. Leonhard, M.‑M. Louërat, H. Aboushady, O. Sinanoglu, Haralampos‑G. Stratigopoulos : “Mixed-Signal IP Protection Against Piracy Based on Logic Locking”, 32. GI / GMM / ITG - Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Ludwigsburg, Germany (2020)
  • A. Pavlidis, M.‑M. Louërat, E. Faehn, A. Kumar, Haralampos‑G. Stratigopoulos : “SymBIST: Symmetry-based Analog/Mixed-Signal BIST”, 32. GI / GMM / ITG - Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Ludwigsburg, Germany (2020)
  • F. Gebreyohannes, J. Porte, M.‑M. Louërat, H. Aboushady : “A g m /I D Methodology Based Data-Driven Search Algorithm For the Design of Multi-Stage Multi-Path Feed-Forward-Compensated Amplifiers Targeting High Speed Continuous-Time Σ∆-Modulators”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (IEEE) (2020)
  • J. Leonhard, A. Sayed, M.‑M. Louërat, H. Aboushady, Haralampos‑G. Stratigopoulos : “Analog and Mixed-Signal IC Security Via Sizing Camouflaging”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (IEEE) (2020)
• 2019
  • J.‑P. Chaput, M.‑M. Louërat, R. Chotin‑Avot, A. Satin : “RISC-V design using Free Open Source Software”, the RISC-V Week, Paris, France (2019)
  • J. Leonhard, M.‑M. Louërat, H. Aboushady, O. Sinanoglu, Haralampos‑G. Stratigopoulos : “Mixed-Signal Hardware Security Using MixLock: Demonstration in an Audio Application”, International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Laussane, Switzerland, pp. 185-188, (IEEE) (2019)
  • F. Gebreyohannes, M.‑M. Louërat, H. Aboushady : “Design of a 4^th-Order Feed-Forward-Compensated Operational Amplifier for Multi-GHz Sampling Frequency Continuous-Time Bandpass Sigma-Delta Modulators”, 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, (IEEE) (2019)
  • J. Leonhard, M. Yasin, Sh. Turk, M. Nabeel, M.‑M. Louërat, R. Chotin‑Avot, H. Aboushady, O. Sinanoglu, Haralampos‑G. Stratigopoulos : “MixLock: Securing Mixed-Signal Circuits via Logic Locking”, Design, Automation and Test in Europe (DATE 2019), Proceedings of the 2019 Design, Automation and Test in Europe, Florence, Italy, pp. 84-89 (2019)
  • J. Porte, M.‑M. Louërat : “From filters to transistors A library of analog schematic with automated sizing Team: FOSS EDA for analog and mixed circuit design”, Free Silicon Conference, Paris, France (2019)
• 2018
  • N. Shimizu, J. Akita, M.‑M. Louërat, Haralampos‑G. Stratigopoulos, J.‑P. Chaput, D. Galayko : “Open Source Hardware and EDA Tools for Analog/Mixed-Signal Design and Prototyping”, 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, (IEEE) (2018)
  • D. Genius, M.‑M. Louërat, F. Pêcheux, L. Apvrille, Haralampos‑G. Stratigopoulos : “Modeling Heterogeneous Embedded Systems with TTool”, DUHDe 2018 — 5^th Workshop on Design Automation for Understanding Hardware Designs, Dresden, Germany (2018)
• 2017
  • E. Lao, M.‑M. Louërat, J.‑P. Chaput : “Highly configurable place and route for analog and mixed-signal circuits”, PhD Forum at Design, Automation and Test in Europe Conference (DATE), Lausanne, Switzerland (2017)
• 2016
  • E. Lao, M.‑M. Louërat, J.‑P. Chaput : “Semi-Automated Analog Placement based on Margin Tolerances”, The 20^th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2016), Kyoto, Japan (2016)
  • E. Lao, M.‑M. Louërat, J.‑P. Chaput : “Semi-automated analog placement”, Electronics, Circuits and Systems (ICECS), 2016 IEEE International Conference on, Monte Carlo, Monaco, pp. 432-433 (2016)
  • H. Zou, Y. Moursy, R. Iskander, J.‑P. Chaput, M.‑M. Louërat : “An Adaptive Mesh Refinement Strategy of Substrate Modeling for Smart Power ICs”, 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, pp. 2358-2361 (2016)
  • Y. Moursy, R. Khalil, S. Lecce, V. Poletto, R. Iskander, M.‑M. Louërat : “Mixed-Signal PI Controller in Current-Mode DC-DC Buck Converter for Automotive Applications”, IEEE International Symposium on Circuits and Systems (ISCAS'16), Montréal, Canada, pp. 1610-1613, (IEEE) (2016)
  • Y. Moursy, H. Zou, R. Khalil, R. Iskander, P. Tisserand, D.‑M. Ton, G. Pasetti, M.‑M. Louërat : “Efficient Substrate Noise Coupling Verification and Failure Analysis Methodology for Smart Power ICs in Automotive Applications”, IEEE Transactions on Power Electronics, (Institute of Electrical and Electronics Engineers) (2016)
  • H. Zou, Y. Moursy, R. Iskander, A. Steinmair, H. Gensinger, Eh. Seebacher, J.‑P. Chaput, M.‑M. Louërat : “Using CAD Tool for Substrate Parasitic Modeling in Smart Power Technology”, IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 2323-2333, (IEEE) (2016)
• 2015
  • C. Ben Aoun, L. Andrade Porras, T. Maehne, F. Pêcheux, M.‑M. Louërat, A. Vachoux : “Pre-Simulation Elaboration of Heterogeneous Systems: The SystemC Multi-Disciplinary Virtual Prototyping Approach”, International Conference on Embedded Computer Systems: Architectures, Modelling and Simulation (SAMOS XV), Samos, Greece, pp. 278-285 (2015)
  • R. Khalil, M.‑M. Louërat, R. Petigny : “Background Analog and Mixed Signal Calibration System For Time-Interleaved ADC”, Microelectronics Journal, vol. 46 (7), pp. 656–667, (Elsevier) (2015)
  • H. Adel, M. Sabut, M.‑M. Louërat : “Split ADC Based Fully Deterministic Multistage Calibration for High Speed Pipeline ADCs”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62 (6), pp. 1481-1488, (IEEE) (2015)
  • H. Adel, M. Sabut, M.‑M. Louërat : “1.1-V 200 Ms/S 12-Bit Digitally Calibrated Pipeline ADC in 40 nm CMOS”, IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, pp. 2281-2284 (2015)
  • B. Vernay, A. Krust, G. Schroepfer, F. Pêcheux, M.‑M. Louërat : “SystemC-AMS Simulation of Biaxial Accelerometer based on MEMS Reduced-Order Modeling”, Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2015, Montpellier, France, pp. 1-6, (IEEE) (2015)
  • M. Barnasconi, M. Dietrich, K. Einwich, Th. Vörtler, J.‑P. Chaput, M.‑M. Louërat, F. Pêcheux, Zh. Wang, Ph. Cuenot, I. Neumann, Th. Nguyen, R. Lucas, E. Vaumorin : “UVM-SystemC-AMS Framework for System-Level Verification and Validation of Automotive Use Cases”, IEEE Design & Test, pp. 76-86, (IEEE) (2015)
  • Y. Li, Zh. Wang, F. Pêcheux, M.‑M. Louërat, M. Barnasconi, Th. Vörtler, K. Einwich : “AMS System-level exploration and verification using UVM in SystemC and SystemC AMS”, 2^nd Workshop Design Automation for Understanding Hardware Designs (DUHDe), Grenoble, France (2015)
  • R. Iskander, F. Javid, M.‑M. Louërat : “Is there a chance that computers understand analog design?”, 2^nd Workshop Design Automation for Understanding Hardware Designs (DUHDe), Grenoble, France (2015)
  • L. Andrade Porras, T. Maehne, A. Vachoux, C. Ben Aoun, F. Pêcheux, M.‑M. Louërat : “Pre-Simulation Symbolic Analysis of Synchronization Issues between Discrete Event and Timed Data Flow Models of Computation”, The 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, pp. 1671-1676 (2015)
  • L. Andrade Porras, C. Ben Aoun, B. Vernay, T. Maehne, F. Pêcheux, M.‑M. Louërat : “Understanding the Heterogeneous Hardware: Do not forget the interconnection!”, 2^nd Workshop Design Automation for Understanding Hardware Designs (DUHDe), Grenoble, France (2015)
  • A. Malak, Y. Li, R. Iskander, F. Durbin, F. Javid, M.‑M. Louërat, A. Tissot, J.‑M. Guebhard : “Fast multidimensional optimization of analog circuits initiated by monodimensional global Peano explorations”, Integration, the VLSI Journal, vol. 48, pp. 198-212, (Elsevier) (2015)
  • H. Zou, Y. Moursy, R. Iskander, J.‑P. Chaput, M.‑M. Louërat, C. Stefanucci, P. Buccella, M. Kayal, J.‑M. Sallese, Th. Gneiting, H. Alius, A. Steinmair, Eh. Seebacher : “A CAD integrated solution of substrate modeling for industrial IC design”, 2015 20^th International Mixed-Signal Testing Workshop (IMSTW), Paris, France (2015)
  • Y. Moursy, R. Iskander, M.‑M. Louërat : “Automated triangular wave generator design with process corners compensation”, Mixed-Signal Testing Workshop (IMSTW), 2015 20^th International, Paris, France, pp. 1-6, (IEEE) (2015)
  • M.‑M. Louërat, T. Maehne : “Languages, Design Methods, and Tools for Electronic System Design: Selected Contributions from FDL 2013”, vol. 311, Lecture Notes in Electrical Engineering (LNEE), (Springer), (ISBN: 978-3-319-06316-4) (2015)
  • Y. Li, H. Zou, Y. Moursy, R. Iskander, R. Sobot, M.‑M. Louërat : “Optimization and Co-Simulation of an Implantable Telemetry System by Linking System Models to Nonlinear Circuits”, chapter in Computational Intelligence in Analog an Mixed-Signal (AMS) and Radio-Frequency (RF) Circuit Design, pp. 83-113, (Springer) (2015)
• 2014
  • T. Maehne, Zh. Wang, L. Andrade Porras, B. Vernay, C. Ben Aoun, J.‑P. Chaput, M.‑M. Louërat, F. Pêcheux, A. Krust, G. Schroepfer, M. Barnasconi, K. Einwich, F. Cenni, O. Guillaume : “UVM-SystemC-AMS based Framework for the Correct by Construction Design of MEMS in their Real Heterogeneous Application Context,”, IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Marseille, France, pp. 862-865 (2014)
  • Th. Vörtler, Th. Klotz, K. Einwich, Y. Li, Zh. Wang, M.‑M. Louërat, J.‑P. Chaput, F. Pêcheux, R. Iskander, M. Barnasconi : “Enriching UVM in SystemC with AMS extensions for randomization and coverage”, Design and Verification Conference and Exhibition (DVCON Europe), Munich, Germany (2014)
  • R. Lucas, E. Vaumorin, Ph. Cuenot, Y. Li, Zh. Wang, M.‑M. Louërat, J.‑P. Chaput, F. Pêcheux, R. Iskander, M. Barnasconi, Th. Vörtler, K. Einwich : “Generation of UVM compliant Test Benches for Automotive Systems using IP-XACT with UVM-SystemC and SystemC AMS extensions”, Design and Verification Conference and Exhibition (DVCON Europe), Munich, Germany (2014)
  • H. Zou, Y. Moursy, R. Iskander, M.‑M. Louërat, J.‑P. Chaput : “A novel CAD framework for substrate modeling”, 10^th Conference on Ph.D Research in Microelectronics and electronics, Grenoble, France, pp. 1-4, (IEEE) (2014)
  • B. Vernay, A. Krust, T. Maehne, G. Schroepfer, F. Pêcheux, M.‑M. Louërat : “Méthode de modélisation haut-niveau de dispositifs MEMS en SystemC-AMS”, Actes du neuvième colloque du GDR SOC-SIP du CNRS, Paris, France, pp. 3 (2014)
  • H. Adel, M. Sabut, R. Petigny, M.‑M. Louërat : “Split ADC digital background calibration for high speed SHA-less pipeline ADCs”, International Symposium on Circuits and Systems (ISCAS), Melbourne, Australia, pp. 1143-1146, (IEEE) (2014)
  • B. Vernay, A. Krust, T. Maehne, G. Schroepfer, F. Pêcheux, M.‑M. Louërat : “A Novel Method of MEMS System-Level Modeling via Multi-Domain Virtual Prototyping in SystemC-AMS”, EDAA/ACM PhD Forum at the Design, Automation and Test in Europe (DATE), Dresden, Germany (2014)
  • Y. Li, R. Iskander, M.‑M. Louërat : “Modeling, Design and Verification Platform using SystemC AMS”, 15^th International Symposium on Quality Electronic Design, ISQED 2014, Santa Clara, CA, United States, pp. 39-46, (IEEE) (2014)
  • Y. Li, Zh. Wang, M.‑M. Louërat, F. Pêcheux, R. Iskander, Ph. Cuenot, M. Barnasconi, Th. Vörtler, K. Einwich : “Virtual Prototyping, Verification and Validation Framework for Automotive Using SystemC, SystemC-AMS and SystemC-UVM”, Embedded Real Time Software and Systems (ERTS2), Toulouse, France, pp. 1-10 (2014)
  • Y. Li, R. Iskander, F. Javid, M.‑M. Louërat : “A Design and Verification Methodology for Mixed-Signal Systems Using SystemC-AMS”, chapter in Models, Methods, and Tools for Complex Chip Design, vol. 265, Lecture Notes in Electrical Engineering, pp. 89-108, (Springer) (2014)
• 2013
  • M.‑M. Louërat : “Circuits analogiques documentés et réutilisables : Synthèse analogique sous l’oeil du concepteur”, habilitation, phd defence 07/03/2013 (2013)
  • H. Adel, M.‑M. Louërat, M. Sabut : “Design Considerations for Low Gain Amplifier in the MDAC of Digitally Calibrated Pipelined ADCs”, IFIP/IEEE 21^st International Conference on Very Large Scale Integration, VLSI-SoC 2013, Istanbul, Turkey, pp. 23-26, (IEEE) (2013)
  • J. Bonan, Ch. Hagleitner, H. Aboushady, M.‑M. Louërat : “Compact and Low power ADCs for a MEMs-based Probe Storage Device”, Analog Integrated Circuits and Signal Processing, vol. 76 (1), pp. 23-34, (Springer Verlag) (2013)
  • L. Andrade Porras, T. Maehne, M.‑M. Louërat, F. Pêcheux : “Time Step Control and Threshold Crossing Detection in SystemC AMS 2.0”, Actes du huitième colloque du GDR SOC-SIP du CNRS, Lyon, France, pp. 3 (2013)
  • Y. Moursy, S. Afara, P. Buccella, C. Stefanucci, R. Iskander, M. Kayal, J.‑M. Sallese, M.‑M. Louërat, J.‑P. Chaput, M. Thomas Tomasevic , S. Ben Dhia, A. Boyer, B. Guegan, V. Poletto, A. Roggero, T. Cavioni, E. Novarini, Eh. Seebacher, A. Steinmair, P. Tisserand, D.‑M. Ton, Th. Bousquet, Th. Gneiting : “AUTOMICS: A novel approach for substrate modeling for Automotive applications”, 18^th IEEE European Test Symposium, Avignon, France (2013)
  • F. Javid, R. Iskander, M.‑M. Louërat, F. Durbin : “A Structured DC Analysis Methodology for Accurate Verification of Analog Circuits”, IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, pp. 2662-2665, (IEEE) (2013)
  • R. Iskander, M.‑M. Louërat, A. Kaiser : “Hierarchical sizing and biasing of analog firm intellectual properties”, Integration, the VLSI Journal, vol. 46 (2), pp. 172-188, (Elsevier) (2013)
  • F. Javid, S. Youssef, R. Iskander, M.‑M. Louërat : “A Designer-Assisted Analog Synthesis Flow”, chapter in Analog/RF and Mixed-Signal Circuit Systematic Design, vol. 233, Lecture Notes in Electrical Engineering, pp. 123-148, (Springer) (2013)
  • F. Pêcheux, M.‑M. Louërat, K. Einwich : “SystemC AMS and Cosimulation Aspects”, chapter in System-level Modeling of MEMS, vol. 10, Advanced Micro and Nanosystems, pp. 357-376, (Wiley) (2013)
• 2012
  • F. Javid, R. Iskander, F. Durbin, M.‑M. Louërat : “Analog Circuits Sizing Using the Fixed Point Iteration Algorithm with Transistor Compact Models”, International Journal of Microelectronics and Computer Science, vol. 3 (1), pp. 7-14, (Department of Microelectronics and Computer Science (DMCS) of Technical University of Łódź) (2012)
  • Y. Li, R. Iskander, F. Javid, M.‑M. Louërat : “A Unified Platform for Design and Verification of Mixed-Signal Systems Based on SystemC-AMS”, Forum on specification & Design Languages, FDL 2012, Vienna, Austria, pp. 75-82 (2012)
  • R. Khalil, M.‑M. Louërat, R. Petigny, H. Gicquel : “Background Offset and Gain Calibration for Time-Interleaved ADC Using Digital Sinusoidal Calibration Signal”, The International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2012, Seville, Spain, pp. 273-276, (IEEE) (2012)
  • F. Javid, S. Youssef, R. Iskander, M.‑M. Louërat : “A Designer Centric Analog Synthesis Flow”, Colloque GDR SOC-SIP, Paris, France, pp. 1-2 (2012)
  • Y. Li, R. Iskander, F. Javid, M.‑M. Louërat : “An Interface between System-level and Circuit-level for Design of Mixed-Signal Systems”, Colloque GDR SOC-SIP, Paris, France, pp. 1-2 (2012)
  • H. Adel, M.‑M. Louërat, M. Sabut : “Background calibration for pipelined ADCs”, Colloque du GDR SOC-SIP du CNRS, Paris, France (2012)
  • R. Khalil, M.‑M. Louërat, R. Petigny, H. Gicquel : “Background Time Skew Calibration for Time-Interleaved ADC Using Phase Detection Method”, IEEE 10^th International New Circuits and Systems Conference (NEWCAS), Montreal, Canada, pp. 257-260 (2012)
  • M. Allam, H. Aboushady, M.‑M. Louërat : “Continuous-Time Sigma Delta Modulators With VCOBased Voltage-to-Phase and Voltage-to-Frequency Quantizers”, Colloque GDR SOC-SIP, Paris, France (2012)
  • F. Javid, R. Iskander, F. Durbin, M.‑M. Louërat : “Analog Circuits Sizing Using the Fixed Point Iteration Algorithm with Transistor Compact Models”, 19^th IEEE International Mixed Design of Integrated Circuits and Systems Conference (MIXDES), Warsaw, Poland, pp. 45-50 (2012)
  • H. Adel, M.‑M. Louërat, M. Sabut : “Fast split background calibration for pipelined ADCs enabled by slope mismatch averaging technique”, Electronics Letters, vol. 48 (6), pp. 318-320, (IET) (2012)
  • A. Lévêque, F. Pêcheux, M.‑M. Louërat, H. Aboushady, F. Cenni, S. Scotti, A. Massouri, L. Clavier : “Holistic Modeling of Embedded Systems with Multi-Discipline Feedback: Application to a Precollision Mitigation Braking System”, Design, Automation and Test in Europe (DATE'12), Dresden, Germany, pp. 739-744, (EDAA Publishing) (2012)
• 2011
  • F. Javid, R. Iskander, M.‑M. Louërat, D. Dupuis : “Analog Circuits Sizing Using Bipartite Graphs”, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Seoul, Korea, Republic of, pp. 1-4 (2011)
  • H. Adel, M.‑M. Louërat, H. Gicquel, M. Sabut : “Low Voltage Techniques for Pipelined A/D Converters”, Colloque GDR SOC SIP, Lyon, France, pp. 1-2 (2011)
  • S. Youssef, D. Dupuis, R. Iskander, M.‑M. Louërat : “Routing Methodology For Nanometric Analog CMOS Devices”, Colloque GDR SOC SIP, Lyon, France, pp. 1-2 (2011)
  • S. Scotti, M. Barnasconi, M.‑M. Louërat, E. Vaumorin : “Design Refinement of Embedded Analogue and Mixed Signal System”, CATRENE DTC conference and EdaForum, Dresden, Germany, pp. 1 (2011)
  • S. Youssef, D. Dupuis, R. Iskander, M.‑M. Louërat : “A Stack-Based Routing Methodology For Nanometric CMOS Devices”, IEEE MOS-AK/GSA Workshop, Paris, France, pp. 1-2 (2011)
  • R. Iskander, M.‑M. Louërat : “Hierarchical Sizing and Biasing of Analog Firm Intellectual Properties”, IEEE MOS-AK/GSA Workshop, Paris, France, pp. 1-2 (2011)
  • M. Abdoallah, M. Dessouky, M.‑M. Louërat, H. Gicquel, A. Shousha : “Pipelined ADC Design Exploration Methodology Employing Circuit-System Refinement”, Electronics, Communications and Photonics Conference, Riyadh, Saudi Arabia, pp. 1-4, (IEEE) (2011)
  • F. Javid, R. Iskander, M.‑M. Louërat, D. Dupuis : “Using Compact MOS Models for Hierarchical Sizing and Biasing of Analog IPs”, IEEE MOS-AK/GSA Workshop, Paris, France, pp. 1-2 (2011)
  • S. Youssef, F. Javid, D. Dupuis, R. Iskander, M.‑M. Louërat : “A Python-Based Layout-Aware Analog Design Methodology For Nanometric Technologies”, IEEE 6^th International Design and Test Workshop (IDT), Beyrouth, Lebanon, pp. 62-67 (2011)
  • S. Youssef, D. Dupuis, R. Iskander, M.‑M. Louërat : “A Stack-Based Routing Methodology For Nanometric Analogue CMOS Devices”, The IEEE Virtual Worldwide Forum For PhD Researchers in Electronic Design Automation, (VW FEDA), Southampton, United Kingdom, pp. 1-6 (2011)
  • S. Youssef, F. Javid, D. Dupuis, R. Iskander, M.‑M. Louërat : “A Seamless Representation for Coupling Transistor Sizing with Nanometric CMOS Layout Generation”, 20^th European Conference on Circuit Theory and Design (ECCTD), Linkoping, Sweden, pp. 341-344 (2011)
• 2010
  • A. Habib, F. Pêcheux, M.‑M. Louërat : “Systemc-ams modeling of a pcr-ce lab-on-chip for multithreaded dna analysis”, 22^nd International Conference on Microelectronics (ICM), Cairo, Egypt, pp. 483-486, (IEEE) (2010)
  • S. Youssef, D. Dupuis, R. Iskander, M.‑M. Louërat : “A Python-Based Analog Layout Generation Tool For Nanometer CMOS Technologies”, Colloque national du GDR SOC-SIP, Cergy, France, pp. 1-2 (2010)
  • F. Javid, R. Iskander, M.‑M. Louërat, D. Dupuis : “A Design Environment for Analog IPs Design Knowledge Capture and Migration”, Colloque GDR SOC-SIP : System-On-Chip, System-In-Package, Paris, France, pp. 1-2 (2010)
  • R. Khalil, M. Allam, R. Iskander, M.‑M. Louërat : “Design and Modeling of 8-Bit Successive Approximation Analog to Digital Converter”, Colloque GDR SOC-SIP : System-On-Chip, System-In-Package, Paris, France, pp. 1-2 (2010)
  • H. Adel, M. Dessouky, M.‑M. Louërat, H. Gicquel, H. Haddara : “Foreground Digital Calibration of Non-Linear Errors in Pipelined A/D Converters”, IEEE International Symposium on Circuits and Systems (ISCAS), Paris, France, pp. 569-572, (IEEE) (2010)
  • A. Lévêque, F. Pêcheux, M.‑M. Louërat, H. Aboushady, M. Vasilevski : “SystemC-AMS Models for Low-Power Heterogeneous Designs: Application to a WSN for the Detection of Seismic Perturbations”, ARCS '10 - 23^th International Conference on Architecture of Computing Systems, Hannover, Germany, pp. 1-6 (2010)
  • Sabiniano A. Rodrigues, H. Aboushady, M.‑M. Louërat, José I. C. Accioly, Raimundo C. S. Freire : “A Clock-less 8-bit folding A/D converter”, IEEE Latin American Symposium on Circuits and Systems (LASCAS), Foz do Iguacu, Brazil, pp. 25-28, (IEEE) (2010)
  • S. Youssef, D. Dupuis, R. Iskander, M.‑M. Louërat : “Automatic Stress Effects Computation Based On A Layout Generation Tool For Analog IC”, 2010 IEEE International Behavioral Modeling and Simulation Conference (BMAS 2010), San Jose, CA, United States, pp. 7-12 (2010)
  • A. Massouri, A. Lévêque, L. Clavier, M. Vasilevski, A. Kaiser, M.‑M. Louërat : “Baseband Fading Channel Simulator for Inter-Vehicle Communication using SystemC-AMS”, 2010 IEEE International Behavioral Modeling and Simulation Conference (BMAS 2010), San Jose, CA, United States, pp. 36-41 (2010)
  • M. Allam, H. Aboushady, M.‑M. Louërat : “Continuous-Time ΣΔ modulators with VCO-Based voltage-to-phase and voltage-to-frequency quantizers”, MWSCAS 2010 - Midwest Symposium on Circuits and Systems, Seattle, United States, pp. 676-679, (IEEE) (2010)
  • W. Gaber, M. Allam, H. Aboushady, M.‑M. Louërat, E.‑S. Eid : “Systematic design of continuous-time ΣΔ modulator with VCO-based quantizer”, ISCAS 2010 - IEEE International Symposium on Circuits and Systems, Paris, France, pp. 29-32, (IEEE) (2010)
• 2009
  • D. Belfort, N. Beilleau, H. Aboushady, M.‑M. Louërat, Sebastian Y. C. Catunda : “A Q-enhanced LC bandpass filter using CAIRO+”, IEEE International Conference on Electronic Circuits and Systems, (ICECS), Hammamet, Tunisia, pp. 860-863, (IEEE) (2009)
  • R. Iskander, M.‑M. Louërat, A. Kaiser : “Design and Analysis of Analog Firm IPs using Hierarchical Sizing and Biasing Methodology”, ESSDERC European Solid-State Device Research Conference, Athens, Greece, pp. 1-2 (2009)
  • F. Javid, R. Iskander, M.‑M. Louërat : “Simulation-Based Hierarchical Sizing and Biasing of Analog Firm IPs”, IEEE International Behavioral Modeling and Simulation Conference (BMAS), San Jose, California, United States, pp. 43-48, (IEEE) (2009)
  • M. Vasilevski, H. Aboushady, M.‑M. Louërat : “Automatic model refinement of GmC integrators for high-level simulation of continuous-time Sigma-Delta modulators”, ISCAS'09 - IEEE International Symposium on Circuits and Systems, Taipei, Taiwan, Province of China, pp. 2769-2772, (IEEE) (2009)
  • R. Iskander, M.‑M. Louërat, A. Kaiser : “Hierarchical Sizing and Biasing of Analog Firm Intellectual Properties”, DATE University Booth, Nice, France, pp. 1-2 (2009)
• 2008
  • R. Iskander, M.‑M. Louërat, A. Kaiser : “Automatic DC operating point computation and design plan generation for analog IPs”, Analog Integrated Circuits and Signal Processing, vol. 56 (1-2), pp. 93-105, (Springer Verlag) (2008)
• 2007
  • R. Iskander, M.‑M. Louërat, A. Kaiser : “Computing Systematic Offsets in Amplifiers Using Hierarchical Graph-Based Sizing and Biasing”, ICM International Conference on Microelectronics, Le Caire, Egypt, pp. 391-394, (IEEE) (2007)
  • R. Iskander, A. Kaiser, M.‑M. Louërat : “Systematic Offset Detection and Evaluation Using Hierarchical Graph-Based Sizing and Biasing”, 14^th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Marrackech, Morocco, pp. 170-173, (IEEE) (2007)
  • R. Iskander, M.‑M. Louërat, A. Kaiser, D. Galayko : “Knowledge-Aware Synthesis Using Hierarchical Graph-Based Sizing and Biasing”, 50^th Midwest Symposium on Circuits and Systems (MWSCAS), Montréal, Québec, Canada, pp. 984-987, (IEEE) (2007)
  • R. Iskander, D. Galayko, M.‑M. Louërat : “Connaissance et Optimisation pour la Synthèse Analogique”, Colloque Groupement de Recherche : System-On-Chip, System-In-Package, GDR SoC SiP, Paris, France, pp. 1-2 (2007)
  • R. Iskander, M.‑M. Louërat, A. Kaiser : “Détection et évaluation des tensions de décalage d’un circuit analogique”, TAISA Colloque sur le Traitement Analogique de l'Information du Signal et ses Applications, Lyon, France, pp. 13-16 (2007)
• 2006
  • L. De Lamarre, M.‑M. Louërat, A. Kaiser : “Optimizing Resistances and Capacitances of a Continuous-Time Sigma-Delta Modulator”, ICECS IEEE International Conference on Electronics Circuits and Systems, Nice, France, pp. 419-422, (IEEE) (2006)
  • D. Galayko, R. Iskander, M.‑M. Louërat, A. Greiner : “Réutilisation et migration d’amplificateurs avec CAIRO+”, JP CNFM Journées pédagogiques du CNFM, Saint Malo, France, pp. 35-39 (2006)
  • R. Iskander, M.‑M. Louërat, A. Kaiser : “Dimensionnement automatique d’un circuit analogique à l’aide des transistors de référence”, TAISA Colloque sur le Traitement Analogique de l'Information du Signal et ses Applications, Strasbourg, France, pp. 89-92 (2006)
  • L. De Lamarre, M.‑M. Louërat, A. Kaiser : “Optimisation des éléments passifs d’un convertisseur sigma-delta temps continu”, TAISA Colloque sur le Traitement Analogique de l'Information du Signal et ses Applications, Strasbourg, France, pp. 101-104 (2006)
  • R. Iskander, M.‑M. Rosset‑Louërat, A. Kaiser : “Hierarchical Graph-Based Sizing for Analog Cells Through Reference Transistors”, PRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics Winner of the Bronze Leaf Certificate, Otranto, Italy, pp. 321-324, (IEEE) (2006)
  • R. Iskander, P. Nguyen‑Tuong, L. De Lamarre, V. Bourguet, M.‑M. Louërat, A. Greiner : “Automated Hierarchical Knowledge-Based Synthesis for Analog Cells using CAIRO+”, Design Automation and Test in Europe Conference (DATE'2006), Munich, Germany (2006)
• 2005
  • R. Iskander, M.‑M. Rosset‑Louërat, A. Kaiser : “Automatic Biasing Point Extraction and Design Plan Generation for Analog IPs”, MWSCAS 2005 - 48^th Midwest Symposium on Circuits and Systems, Cincinnati, Ohio, United States, pp. 907-910, (IEEE) (2005)
  • N. Beilleau, H. Aboushady, M.‑M. Rosset‑Louërat : “Using Finite Impulse Response Feedback DACs to design Sigma-Delta modulators based on LC filters”, MWSCAS 2005 - 48^th Midwest Symposium on Circuits and Systems, Cincinnati, Ohio, United States, pp. 696-699, (IEEE) (2005)
  • L. De Lamarre, M.‑M. Rosset‑Louërat, A. Kaiser : “A simple 3.8mW, 300 MHz, 4-bit flash analog-to-digital converter”, Microtechnologies for the New Millennium 2005 VLSI Circuits and Systems II, vol. 5837, SPIE Proceedings, Sevilla, Spain, pp. 825-832, (The International Society for Optical Engineering) (2005)
  • D. Khalil, M. Dessouky, V. Bourguet, M.‑M. Rosset‑Louërat, A. Cathelin, H. Ragai : “Evaluation of Capacitor Ratios in Automated Accurate Common-Centroid Capacitor Arrays”, ISQED 2005 - 6^th International Symposium on Quality of Electronic Design, San Jose, California, United States, pp. 143-147, (IEEE) (2005)
  • R. Iskander, L. De Lamarre, P. Nguyen‑Tuong, M.‑M. Louërat, A. Kaiser : “Synthèse d’un IP amplificateur analogique CMOS avec CAIRO+”, TAISA 2005 - 6^e Colloque sur le Traitement Analogique de l'Information du Signal et ses Applications, Marseille, France, pp. 69-72 (2005)
  • L. De Lamarre, M.‑M. Louërat, A. Kaiser : “Un convertisseur flash 4 bits à base de transistors MOS consommant 3,8mW à 300MHz”, TAISA 2005 - 6^e Colloque sur le Traitement Analogique de l'Information du Signal et ses Applications, Marseille, France, pp. 57-60 (2005)
• 2004
  • V. Bourguet, L. De Lamarre, M.‑M. Rosset‑Louërat : “Analog IC Design with a Library of Parameterized Device Generators”, DCIS International Conference on Design of Circuits and Integrated Systems, Bordeaux, France, pp. 739-744 (2004)
  • P. Nguyen‑Tuong, M.‑M. Rosset‑Louërat, A. Greiner : “Guidelines for Designing Smart and Reusable Analog IP Cores”, Sophia Antipolis MicroElectronics Forum (SAME), Sophia Antipolis, France, pp. 1-6 (2004)
  • P. Nguyen‑Tuong, V. Bourguet, L. De Lamarre, M.‑M. Rosset‑Louërat, A. Greiner : “A Language to Design Generators of Analog Functions”, FDL 2004 - Forum on Specification & Design Languages, Lille, France, pp. 30-31 (2004)
  • D. Khalil, M. Dessouky, V. Bourguet, M.‑M. Rosset‑Louërat, A. Cathelin, H. Ragai : “Compensated Layout for Automated Accurate Common-Centroid Capacitor Arrays”, ICEEC 2004 - International Conference on Electrical Electronic and Computer Engineering, Cairo, Egypt, pp. 481-484 (2004)
  • R. Iskander, L. De Lamarre, A. Kaiser, M.‑M. Rosset‑Louërat : “Design Space Exploration for Analog IPs using CAIRO+”, ICEEC 2004 - International Conference on Electrical Electronic and Computer Engineering, Cairo, Egypt, pp. 473-476, (IEEE) (2004)
  • V. Bourguet, L. De Lamarre, M.‑M. Rosset‑Louërat : “A Layout-Educated Analog Design Flow”, MWSCAS 2004 - 47^th Midwest Symposium on Circuits and Systems, Hiroshima, Japan, pp. 432-488 (2004)
  • H. Aboushady, L. De Lamarre, N. Beilleau, M.‑M. Rosset‑Louërat : “A Mixed Equation-based and Simulation-based Design Methodology for Continuous-Time Sigma-Delta Modulators”, MWSCAS 2004 - 47^th Midwest Symposium on Circuits and Systems, Hiroshima, Japan, pp. 109-112, (IEEE) (2004)
  • N. Beilleau, H. Aboushady, M.‑M. Rosset‑Louërat : “Filtering Adjacent Channel Blockers using Signal-Transfer-Function of Continuous-Time Sigma-Delta Modulators”, MWSCAS 2004 - 47^th Midwest Symposium on Circuits and Systems, Hiroshima, Japan, pp. 329-332, (IEEE) (2004)
  • P. Nguyen‑Tuong, M.‑M. Rosset‑Louërat, A. Greiner : “Managing the Shape Function of Analog Devices in a Slicing Tree Floorplan”, Mixed Design of Integrated Circuits and Systems (MIXDES), Szczecin, Poland, pp. 226-229 (2004)
  • H. Aboushady, M.‑M. Rosset‑Louërat : “Loop Delay Compensation in Bandpass Continuous-Time Modulators without Additional Feedback Coefficients”, IEEE International Symposium on Circuits and Systems (ISCAS), Vancouver, Canada, pp. 1124-1127, (IEEE) (2004)
  • H. Aboushady, L. De Lamarre, N. Beilleau, M.‑M. Rosset‑Louërat : “Automatic Synthesis and Simulation of Continuous-Time Sigma Delta Modulators”, DATE 2004 - Design Automation and Test in Europe Conference, Paris, France, pp. 674-675, (IEEE) (2004)
• 2003
  • J. Bonan, H. Aboushady, M.‑M. Rosset‑Louërat : “A 3mW, 250 MSamples/sec, 4-bit Current Mode FLASH Analog-to-Digital Converter”, MidWest Symposium on Circuits And Systems 2003 (MWSCAS'03), vol. 1, Le Caire, Egypt, pp. 1-4, (IEEE) (2003)
  • N. Beilleau, H. Aboushady, M.‑M. Rosset‑Louërat : “Systematic Approach for Scaling Coefficients of Discrete-Time and Continuous-Time Sigma-Delta Modulators”, MidWest Symposium on Circuits And Systems (MWSCAS'03), vol. 1, Le Caire, Egypt, pp. 233-236, (IEEE) (2003)
• 2002
  • V. Bourguet, M.‑M. Louërat, A. Greiner : “Composants analogiques déformables pour CAIRO+”, Troisième colloque du GDR CAO de circuits et systèmes intégrés, Paris, France, pp. 25-28 (2002)
  • T. Nguyen, M.‑M. Louërat, A. Greiner : “Placement Optimal d’Objets Déformables dans l’Environnement de Conception Analogique CAIRO+”, Troisième Colloque du GDR CAO de circuits et systèmes intégrés, Paris, France, pp. 29-32 (2002)
  • H. Aboushady, M.‑M. Louërat : “Systematic Approach for Discrete-Time to Continuous-Time Transformation of Sigma-Delta Modulators”, IEEE International Symposium on Circuits and Systems (ISCAS'2002), Phoenix, AZ, United States, pp. 229-232, (IEEE) (2002)
  • G. Avot, A. Greiner, M.‑M. Louërat, K. Dioury, A. Lester, A. Debreil : “Use of MutiPhase Stability Intervals to handle Crosstalk with the Timing Analyzer hiTas”, Design Automation and Test in Europe Conference (DATE'2002), Paris, France, pp. 112-116 (2002)
  • M.‑M. Louërat : “CAIRO+ : Composants Analogiques Réutilisables”, Journées thématiques du LIP6 : Outils et Méthodes de Conception des Systèmes Intégrés sur Puce, Paris, France (2002)
• 2001
  • H. Aboushady, Y. Dumonteix, M.‑M. Louërat, H. Mehrez : “Efficient Polyphase decomposition of Comb decimation filters in sigma-delta analog-to-digital converters”, IEEE Transactions on Circuits and Systems Part 2 Analog and Digital Signal Processing, vol. 48 (10), pp. 898-903, (Institute of Electrical and Electronics Engineers (IEEE)) (2001)
  • M. Dessouky, M.‑M. Louërat, A. Kaiser : “Switch Sizing for Very Low-Voltage Switched-Capacitor Circuits”, ICECS 2001 - 8^th IEEE International Conference on Electronics, Circuits and Systems, Malta, Malta, pp. 1549-1552, (IEEE) (2001)
  • H. Aboushady, M.‑M. Louërat : “Systematic Design of High-Linearity Current-Mode Integrators for Low-Power Continuous-Time Sigma-Delta Modulators”, IEEE International Conference on Electronic Circuits and Systems (ICECS'2001), vol. 2, Malta, Malta, pp. 963-966, (IEEE) (2001)
  • G. Avot, M.‑M. Louërat : “Models for delay estimation taking into account both cross-talk and wire resistance for timing analysis”, Mixed Design of Integrated Circuits and Systems (MIXDES'2001), Zakopane, Poland, pp. 377-382 (2001)
  • H. Aboushady, M.‑M. Rosset‑Louërat : “Low-Power Design of Low-Voltage Current-Mode Integrators for Continuous-Time Sigma-Delta Modulators”, IEEE International Symposium on Circuits and Systems (ISCAS'2001), Sydney, Australia, pp. 276-279, (IEEE) (2001)
  • M. Dessouky, A. Kaiser, M.‑M. Louërat, A. Greiner : “Analog Design for Reuse - Case Study : Very Low Voltage Delta-Sigma Modulators”, Design Automation and Test in Europe (DATE), Munich, Germany, pp. 353-360, (IEEE) (2001)
• 2000
  • Y. Dumonteix, H. Aboushady, H. Mehrez, M.‑M. Rosset‑Louërat : “Low-power Comb Decimation Filter Using Polyphase Decomposition For Mono-bit Sigma-Delta Analog-to-Digital Converters”, International Conference On Signal Processing Applications and Technologies (ICSPAT 2000), vol. 1, Dallas, Texas, United States, pp. 432-435 (2000)
  • H. Aboushady, Y. Dumonteix, M.‑M. Rosset‑Louërat, H. Mehrez : “Efficient Polyphase Decomposition of Comb Decimation Filters in Sigma-Delta Analog-to-Digital Converters”, 43^rd IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2000), Lansing, MI, United States, pp. 432-435, (IEEE) (2000)
  • M. Dessouky, M.‑M. Rosset‑Louërat : “A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits”, 1^st International Symposium on Quality Electronic Design (ISQED 2000), San Jose, CA, United States, pp. 291-298, (IEEE) (2000)
  • K. Dioury, A. Lester, A. Debreil, G. Avot, A. Greiner, M.‑M. Rosset‑Louërat : “Hierarchical Static Timing Analysis at Bull with HiTas”, Design Automation and Test in Europe Conference User Forum (DATE'2000), Paris, France, pp. 55-60 (2000)
  • M. Dessouky, M.‑M. Rosset‑Louërat, J. Porte : “Layout-Oriented Synthesis of High Performance Analog Circuits”, Design Automation and Test in Europe Conference (DATE'2000), Paris, France, pp. 53-57, (IEEE) (2000)
• 1999
  • M. Dessouky, A. Greiner, M.‑M. Rosset‑Louërat : “CAIRO : A hierarchical layout language for analog circuits”, Mixed Design of Integrated Circuits and Systems (MIXDES'99), Krakow, Poland, pp. 105-110 (1999)
  • M. Dessouky, J. Porte, M.‑M. Rosset‑Louërat : “Synthèse de circuits faible tension CMOS analogiques”, 2^e Journées Francophones d'études Faible Tension Faible Consommation (FTFC'99), Paris, France, pp. 126-130 (1999)
  • M. Dessouky, J. Porte, M.‑M. Rosset‑Louërat : “TANIS : Un outil pour la synthèse de circuits CMOS analogiques”, Colloque CAO de Circuits Intégrés et Systèmes GDR 732, Aix-en-Provence, France, pp. 186-189 (1999)
  • K. Dioury, A. Greiner, M.‑M. Rosset‑Louërat : “Hierarchical Static Timing Analysis for CMOS ULSI Circuits”, International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU'99), Monterey, CA, United States, pp. 65-70 (1999)
  • G. Avot, M.‑M. Rosset‑Louërat : “Influence et prise en compte des capacités de diaphonies dans la conception d’outils d’analyse temporelle pour les technologies profondément submicroniques.”, Colloque CAO de Circuits Intégrés et Systèmes GDR 732, Aix-en-Provence, France, pp. 232-235 (1999)
• 1998
  • M. Dessouky, J. Porte, A. Greiner, M.‑M. Rosset‑Louërat : “Synthèse de Circuits Analogiques CMOS”, 1^ère Journée Nationale Réseau Doctoral Microélectronique, Toulouse, France (1998)
• 1997
  • K. Dioury, A. Greiner, M.‑M. Rosset‑Louërat : “Accurate static timing analysis for deep submicronic CMOS circuits”, International Conference on Very Large Scale Integration (VLSI'97), IFIP - The International Federation for Information Processing, Gramado, Brazil, pp. 439-450, (Springer) (1997)
  • K. Dioury, A. Greiner, M.‑M. Rosset‑Louërat : “Analyse Temporelle des Circuits VLSI à Haute Densité d’Intégration Utilisant des Technologies Submicroniques”, 1^er Colloque CAO de Circuits Intégrés et Systèmes, Grenoble, France, pp. 184-187 (1997)
  • M. Dessouky, A. Greiner, M.‑M. Rosset‑Louërat : “CAIRO : Un Langage pour le Layout Analogique Symbolique”, 1^er Colloque CAO de Circuits Intégrés et Systèmes, Grenoble, France, pp. 14-17 (1997)