Team : ALSOC - Hardware and Software for Embedded System
Axes : ASN (👥👥), SSR (👥👥), TMC (👥).Team leader :
Alix Munier Campus Pierre et Marie Curie 24-25/418
No event planned at present.
Short presentation
The activities of the ALSOC team concern methods and tools for multiprocessors system on chip design, with a focus on manycore architectures. Such highly integrated multiprocessors architectures are used in embedded applications such as automotive, nomad, audio & video, and telecom. The design of these systems requires the development of hardware and software co-design methods. We focus on advanced hardware architecture, communication protocols, embedded operating system, real-time constraints, formal methods for verification systems and optimization of code generation.
system on chip, multiprocessors, manycores, SIMD, GPU, embedded floating point format, embedded operating system, test, verification, compilation, code optimization, SDF
Selected publications
- F. Lemaitre, B. Couturier, L. Lacassagne : “Cholesky Factorization on SIMD multi-core architectures” Journal of Systems Architecture, (Elsevier)[Lemaitre 2017]
- D. Genius, L. Li, L. Apvrille : “Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design” Modeling Languages, Tools and Architectures, Methodologies, Processes and Platforms, Applications and Software Development (MODELSWARD), Porto, Portugal[Genius 2017b]
- H. Liu, Quentin L. Meunier, A. Greiner : “Decoupling Translation Lookaside Buffer Coherence from Cache Coherence” IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2017), Bochum, Germany, pp. 92-97, (IEEE)[Liu 2017]
- H. Bel Hadj Amor, A. Sheibanyrad, F. Pétrot : “A Meta-Routing Method to Create Multiple Virtual Logical Networks on a Single Hardware NoC” 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Bochum, Germany, pp. 200-205, (IEEE)[Bel Hadj Amor 2017b]
- L. Cabaret, L. Lacassagne, D. Etiemble : “Parallel Light Speed Labeling: an efficient connected component algorithm for labeling and analysis on multi-core processors” Journal of Real-Time Image Processing, vol. 15 (1), pp. 173-196, (Springer Verlag)[Cabaret 2018]
- A. Drebes, A. Pop, K. Heydemann, A. Cohen, N. Drach : “Scalable Task Parallelism for NUMA: A Uniform Abstraction for Coordinated Scheduling and Memory Management” PACT'16 - ACM/IEEE Conference on Parallel Architectures and Compilation Techniques, Haifa, Israel, pp. 125-137[Drebes 2016b]
- P. VIVET, Y. Thonnart, R. Lemaire, C. Santos, E. Beigne, Ch. Bernard, F. Darve, D. Lattard, I. Miro‑Panades, D. Dutoit, F. Clermidy, S. Chéramy, A. Sheibanyrad, F. Pétrot, E. Flamand, J. Michailos, A. Arriordaz, L. Wang, J. Schloeffel : “A 4 x 4 x 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links” IEEE Journal of Solid-State Circuits, vol. 52 (1), pp. 33-49, (Institute of Electrical and Electronics Engineers)[VIVET 2016]
- C. Dévigne, J.‑B. Bréjon, Quentin L. Meunier, F. Wajsbürt : “Executing Secured Virtual Machines within a Manycore Architecture” Microprocessors and Microsystems: Embedded Hardware Design, (Elsevier)[Dévigne 2016]
- B. Bodin, A. Munier‑Kordon, B. Dupont De Dinechin : “Optimal and fast throughput evaluation of CSDF” Design Automation Conference DAC, Austin, United States, pp. 160, (ACM)[Bodin 2016]
- A. Carlier, A. Munier‑Kordon, W. Klaudel : “Mathematical Model for the Study of Relocation Strategies in One-way Carsharing Systems” Transportation Research Procedia, vol. 10, pp. 374-383, (Elsevier)[Carlier 2015a]
- N. Moro, K. Heydemann, E. Encrenaz, B. Robisson : “Formal verification of a software countermeasure against instruction skip attacks” Journal of Cryptographic Engineering, vol. 4 (3), pp. 145-156, (Springer)[Moro 2014c]