Équipes actuelles : | ALMASTY ALSOC APR BD CIAN ComplexNetworks DECISION DELYS LFI MOCAH MoVe NPA PEQUAN PolSys QI RO SMA SYEL |
Ancienne équipe : | ACASA |
- A. Andriahantenaina, A. Greiner : “Micro-network for SoC: Implementation of a 32-port SPIN network”, Design Automation and Test in Europe Conference (DATE'2003), Munich, Germany, pp. 1128-1129, (IEEE) [Andriahantenaina 2003a]
- A. Andriahantenaina, H. Charlery, A. Greiner, L. Mortiez, C. Zeferino : “SPIN: a Scalable, Packet Switched, On-Chip Micro-network”, Design Automation and Test in Europe Conference (DATE'2003) Embedded Software Forum, Munich, Germany, pp. 70-73, (IEEE) [Andriahantenaina 2003b]
- I. Augé, F. Donnet, F. Pétrot : “Retiming Finite State Machines to Control Hardened Data-Paths”, SBCCI 2003 - 16th Symposium on Integrated Circuits and Systems Design, Sao Paulo, Brazil, pp. 41-47, (IEEE) [Augé 2003]
- P. Bazargan Sabet, P. Renault : “An Event-Driven Approach to Crosstalk Noise Analysis”, 36th Annual Simulation Symposium (ANSS'36), Orlando, FL, United States, pp. 319-326, (IEEE) [Bazargan Sabet 2003a]
- P. Bazargan Sabet, P. Renault : “Using Symbolic Simulation to Exhibit Worst Case Crosstalk”, 4th IEEE Latin-American Test Workshop (LATW'03), Natal, Brazil, pp. 264-268 [Bazargan Sabet 2003b]
- V. Beaudenon, E. Encrenaz, J.‑L. Desbarbieux : “Design Validation of ZCSP with SPIN”, IEEE Third International Conference on Application of Concurrency to System Design (ACSD 2003), Guimaraes, Portugal, pp. 102-110, (IEEE) [Beaudenon 2003b]
- N. Beilleau, H. Aboushady, M.‑M. Rosset‑Louërat : “Systematic Approach for Scaling Coefficients of Discrete-Time and Continuous-Time Sigma-Delta Modulators”, MidWest Symposium on Circuits And Systems (MWSCAS'03), vol. 1, Le Caire, Egypt, pp. 233-236, (IEEE) [Beilleau 2003]
- J. Bonan, H. Aboushady, M.‑M. Rosset‑Louërat : “A 3mW, 250 MSamples/sec, 4-bit Current Mode FLASH Analog-to-Digital Converter”, MidWest Symposium on Circuits And Systems 2003 (MWSCAS'03), vol. 1, Le Caire, Egypt, pp. 1-4, (IEEE) [Bonan 2003]
- T. Bossart, A. Munier‑Kordon, F. Sourd : “Optimisation de l'utilisation de la mémoire pour un simulateur de circuits”, 5ème Congrès de la Société Française de Recherche Opérationnelle et d'Aide à la Décision (ROADEF 2003), Avignon, France, pp. 393-394 [Bossart 2003a]
- T. Bossart, A. Munier‑Kordon, F. Sourd : “Optimisation de l'utilisation de la mémoire pour un simulateur de circuits”, 5ème Congrès de la Société Française de Recherche Opérationnelle et d'Aide à la Décision (ROADEF 2003), Avignon, France, pp. 393-394 [Bossart 2003b]
- H. Charlery, E. Encrenaz, A. Greiner, A. Andriahantenaina, L. Mortiez : “SPIN, un micro-réseau d'interconnexion à commutation de paquets respectant la norme VCI. Concepts généraux et validation.”, Symposium en Architecture et Adequation Algorithme Architecture (SympAAA 2003), La Colle sur Loup, France, pp. 337-344 [Charlery 2003]
- R. Chotin‑Avot, H. Mehrez : “Hardware implementation of discrete stochastic arithmetic”, 6th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'03), Poznan, Poland, pp. 57-64 [Chotin-Avot 2003a]
- R. Chotin‑Avot, J.‑M. Chesneaux, J.‑L. Lamotte : “On the computation of the CESTAC function”, Real Numbers and Computers 5 (RNC5), Lyon, France, pp. 247-260 [Chotin-Avot 2003b]
- R. Chotin‑Avot, J.‑M. Chesneaux, J.‑L. Lamotte : “On the computation of the CESTAC function”, Real Numbers and Computers 5 (RNC5), Lyon, France, pp. 247-260 [Chotin-Avot 2003c]
- R. Daouphars, L.‑S. Didier : “Use of multiple number representation in automatic arithmetic data-path design”, Advanced Signal Processing Algorithms, Architectures, and Implementations XIII, vol. 5205, San Diego, California, United States, pp. 482-489, (SPIE) [Daouphars 2003a]
- R. Daouphars, L.‑S. Didier : “Use of multiple number representation in automatic arithmetic data-path design”, Advanced Signal Processing Algorithms, Architectures, and Implementations XIII, vol. 5205, San Diego, California, United States, pp. 482-489, (SPIE) [Daouphars 2003b]
- A. Munier‑Kordon : “Variants of the two machine flow-shop with precedence constraints”, MAPSP 2003 - 6th Workshop on Methods and Algorithms for Planning and Scheduling Problems, Aussois, France [Munier-Kordon 2003a]
- F. Pétrot, P. Gomez : “Lightweight Implementation of the POSIX Threads API for an On-Chip MIPS Multiprocessor with VCI Interconnect”, Design Automation and Test in Europe Conference (DATE'2003) Embedded Software Forum, Munich, Germany, pp. 51-56, (IEEE) [Pétrot 2003a]
- C. Roux, E. Encrenaz : “CTL May Be Ambiguous When Model Checking Moore Machines”, CHARME 2003 - 12th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods, vol. 2860, Lecture Notes in Computer Science, L'Aquila, Italy, pp. 164-169, (Springer) [Roux 2003]