Équipes actuelles : | ALMASTY ALSOC APR BD CIAN ComplexNetworks DECISION DELYS LFI MOCAH MoVe NPA PEQUAN PolSys QI RO SMA SYEL |
Ancienne équipe : | ACASA |
- M. Aberbour, H. Mehrez : “Architecture and design Methodology of the RBF-DDA Neural Network”, IEEE International Symposium on Circuits and Systems (ISCAS'98), vol. 3, Monterey, CA, United States, pp. 199-202, (IEEE) [Aberbour 1998b]
- M. Aberbour, H. Mehrez, F. Durbin, Th. Garié, A. Tissot : “Algorithms and VLSI Architectures for Pattern Recognition Based on the Gabor Wavelets”, International Conference on Signal Processing Applications and Technology (ICSPAT'98), Toronto, Canada, pp. 1455-1459 [Aberbour 1998c]
- M. Aberbour, H. Mehrez, F. Durbin, Th. Garié, A. Tissot : “System Level Design of a Pattern Recognition System Based on the Gabor Wavelets”, IEEE-SP Conference on Time-Frequency Time-Scale Analysis (TFTS'98), Pittsburgh, PA, United States, pp. 237-240, (IEEE) [Aberbour 1998d]
- F. Alves Barbosa da Silva, M. Campos, I. Scherson : “A Lower Bound for Dynamic Scheduling of Data Parallel Programs”, 4th International Euro-Par Conference, vol. 1470, Lecture Notes in Computer Science, Southampton, United Kingdom, pp. 367-372, (Springer) [Alves Barbosa da Silva 1998a]
- F. Alves Barbosa da Silva, M. Campos, I. Scherson : “Improvements in Gang Scheduling for Parallel Supercomputers”, 8th International Parallel Computing Workshop, Singapore, Singapore [Alves Barbosa da Silva 1998b]
- Y. Body, F. Dromard, A. Greiner, M.‑M. Paget, F. Pétrot : “SIMIPS : a cycle-precise interactive simulator for teaching microprocessor architecture”, Fourth International Conference on Computer Aided Learning and Instruction in Science and Engineering (CALISCE'98), Götborg, Sweden, pp. 146-154 [Body 1998]
- P. Bukovjan, M. Marzouki, W. Maroufi : “Allocation for Testability in High-Level Synthesis Process”, 5th Electronic Devices and Systems Conference, Brno, Czechia [Bukovjan 1998a]
- P. Bukovjan, M. Marzouki, W. Maroufi : “Cost/Quality Trade-off in High-Level Synthesis for Testability”, 2nd International Workshop on Design and Diagnostics of Electronic Circuits and Systems, Szczyrk, Poland [Bukovjan 1998b]
- M. Dessouky, J. Porte, A. Greiner, M.‑M. Rosset‑Louërat : “Synthèse de Circuits Analogiques CMOS”, 1ère Journée Nationale Réseau Doctoral Microélectronique, Toulouse, France [Dessouky 1998]
- P. Faudemay : “Multidimensional navigation in collections of multimedia objects”, ACM Conference on Computer Human Interfaces (CHI'98), Los Angeles, CA, United States [Faudemay 1998]
- A. Fenyö, P. David, A. Greiner : “Noyau de communication sécurisé pour la machine parallèle MPC”, 10èmes Rencontres sur le Parallélisme (RENPAR'10), Strasbourg, France [Fenyö 1998]
- A. Guettaf, P. Bazargan Sabet : “Efficient Partitioning Method for Distributed Logic Simulation of VLSI Circuits”, 31st Annual Simulation Symposium, Boston, MA, United States, pp. 196-201, (IEEE) [Guettaf 1998a]
- A. Guettaf, P. Bazargan Sabet : “Using Node Replication to Improve Circuit's Partition in Distributed Logic Simulation”, 12th European Simulation Multiconference, Manchester, United Kingdom, pp. 235-237 [Guettaf 1998b]
- D. Hommais : “Un environnement de simulation pour systèmes embarqués”, 1ère Journée Nationale Réseau Doctoral Microélectronique, Toulouse, France [Hommais 1998a]
- D. Hommais, F. Pétrot : “Efficient Combinational Loops Handling for Cycle Precise Simulation of System on a Chip”, 24th EUROMICRO International Conference on Digital Sytems, Vasteras, Sweden, pp. 51-54, (IEEE) [Hommais 1998b]
- L. Jacomme, F. Pétrot, Rajesh K. Bawa : “Formal Extraction of Memorizing Elements for Sequential VHDL Synthesis”, IEEE/EUROMICRO'98 International Conference on Digital Sytems, Vasteras, Sweden, pp. 317-320, (IEEE) [Jacomme 1998]
- A. Lester, P. Bazargan Sabet, A. Greiner : “Circuit Disassembly for Verification and functional Abstraction of CMOS Circuits”, Sophia Antipolis forum on MicroElectronics (SAME'98), Sophia Antipolis, France, pp. 60-63 [Lester 1998a]
- A. Lester, P. Bazargan Sabet, A. Greiner : “YAGLE, a Second generation Functional Abstractor for CMOS VLSI Circuits”, 10th International Conference on Microelectronics (ICM'98), Monastir, Tunisia, pp. 265-268, (IEEE) [Lester 1998b]
- W. Maroufi, M. Marzouki : “STA : A System Testability Assistant”, 3rd IEEE European Test Workshop, Sitges, Spain [Maroufi 1998a]
- W. Maroufi, M. Marzouki : “System Testability Evaluation with STA”, 10th International Conference on Microelectronics (ICM'98), Monastir, Tunisia, pp. 79-81, (IEEE) [Maroufi 1998b]
- O. Oliaei, H. Aboushady : “Jitter Effects in Continuous-Time Sigma-Delta Modulators with Delayed Return-to-Zero Feedback”, 5th IEEE International Conference on Electronics Circuits and Systems (ICECS'98), Lisbon, Portugal, pp. 351-354, (IEEE) [Oliaei 1998]
- F. Rahim, E. Encrenaz, M. Minoux, Rajesh K. Bawa : “Modular Model Checking of VLSI Designs described in VHDL”, IEEE International Conference on Computer and their Applications, Honolulu, Hawai, United States, pp. 365-368 [Rahim 1998a]
- F. Rahim, Rajesh K. Bawa, A. Amara : “VHDL based Verification of RISC pipelined Processor INFINTY : A Case Study”, IEEE/ACM International Workshop on Logic Synthesis (IWLS'98), Lake Tahoe, United States [Rahim 1998b]
- C. Seyrat, G. Durand, P. Faudemay : “Méthode d'indexation multimédia fondée sur les Objets Visuels”, 4èmes Journées d'Echanges Compression et Représentation des Signaux Audiovisuels (CORESA'98), Lannion, France [Seyrat 1998]
- A. Turier, L. Ben Ammar, A. Amara : “An Accurate Power and Timing Modeling Technique Applied to A Low-Power ROM Compiler”, Power and Timing Modeling for Performance of Integrated cicuits (PATMOS'98), Lyngby, Denmark, pp. 181-190 [Turier 1998]
- L. Vuillemin : “Vérification logico-temporelle de circuit VLSI a l'aide d'un réseau de FPGA”, 1ère Journée Nationale Réseau Doctoral Microélectronique, Toulouse, France [Vuillemin 1998]