Équipes actuelles : | ALMASTY ALSOC APR BD CIAN ComplexNetworks DECISION DELYS LFI MOCAH MoVe NPA PEQUAN PolSys QI RO SMA SYEL |
Ancienne équipe : | ACASA |
- N. Abdallah, P. Bazargan Sabet : “Technique de Simulation Event-Driven en Vue d'une Simulation Mixte Efficace”, 1er Colloque CAO de Circuits Intégrés et Systèmes, Grenoble, France, pp. 22-25 [Abdallah 1997a]
- N. Abdallah, P. Bazargan Sabet, J. Dunoyer : “SWISSE: A Fast Switch-Level Timing Simulator with Slope Effects for Large Digital MOS Circuits”, 4th IEEE International Conference on Electronics Circuits and Systems (ICECS'97), Cairo, Egypt, pp. 875-879 [Abdallah 1997b]
- M. Aberbour, A. Derieux, H. Mehrez, N. Vaucher : “Teaching the design of a chip under the Cadence Opus environment using the Alliance cell libraries”, MSE '97 - IEEE International Conference on Microelectronic Systems Education, Arlington, VA, United States, pp. 81-82, (IEEE Computer Society) [Aberbour 1997a]
- M. Aberbour, A. Houelle, H. Mehrez, N. Vaucher, A. Guyot : “A time driven adder generator architecture”, 9th IFIP International Conference on Very Large Scale Integration (VLSI'97), Gramado, RS, Brazil, pp. 453-463, (Springer) [Aberbour 1997b]
- M. Aberbour, F. Ahmad, H. Mehrez : “A Hardware Implementation of an RBF Neural Network : Architecture and Design Methodology”, International Conference on Signal Processing and Technology 97, vol. 3, San Diego, CA, United States, pp. 199-202 [Aberbour 1997c]
- I. Augé, Rajesh K. Bawa, P. Guerrier, A. Greiner, L. Jacomme, F. Pétrot : “User Guided High Level Synthesis”, International Conference on Very Large Scale Integration (VLSI'97), IFIP - The International Federation for Information Processing, Gramado, Brazil, pp. 464-475, (Springer) [Augé 1997]
- L. Chen, D. Donsez, P. Faudemay : “Design of U-Doc, a research vehicle for hyper document retrieval on the Internet”, BIWIT '97 - Third Basque International Workshop on Information Technology, Biarritz, France, pp. 103-110, (IEEE) [Chen 1997a]
- L. Chen, P. Faudemay : “Multicriteria video segmentation for TV news”, First IEEE Workshop on Multimedia Signal Processing, Boston, Massachusets, United States [Chen 1997b]
- M. Dessouky, A. Greiner, M.‑M. Rosset‑Louërat : “CAIRO : Un Langage pour le Layout Analogique Symbolique”, 1er Colloque CAO de Circuits Intégrés et Systèmes, Grenoble, France, pp. 14-17 [Dessouky 1997]
- K. Dioury, A. Greiner, M.‑M. Rosset‑Louërat : “Accurate static timing analysis for deep submicronic CMOS circuits”, International Conference on Very Large Scale Integration (VLSI'97), IFIP - The International Federation for Information Processing, Gramado, Brazil, pp. 439-450, (Springer) [Dioury 1997a]
- K. Dioury, A. Greiner, M.‑M. Rosset‑Louërat : “Analyse Temporelle des Circuits VLSI à Haute Densité d'Intégration Utilisant des Technologies Submicroniques”, 1er Colloque CAO de Circuits Intégrés et Systèmes, Grenoble, France, pp. 184-187 [Dioury 1997b]
- J. Dunoyer, F. Pétrot, L. Jacomme : “Intrinsic Limitations of Logarithmic Encodings for Low Power Finite State Machines”, Mixed Design of VLSI Circuits Conference, Poznan, Poland, pp. 613-618 [Dunoyer 1997a]
- J. Dunoyer, F. Pétrot, L. Jacomme : “Limitations of Logarithmic Encodings for Low Power Finite State Machines”, 4th IEEE International Conference on Electronics Circuits and Systems (ICECS'97), Cairo, Egypt, pp. 522-528 [Dunoyer 1997b]
- J. Dunoyer, F. Pétrot, L. Jacomme : “Stratégie de codage des automates pour les applications basse-consommation : expérimentations et interprétation”, Journées Faible Tension Faible Consommation, Paris, France [Dunoyer 1997c]
- J. Dunoyer, L. Vuillemin, P. Bazargan Sabet : “Méthodes Probabilistes pour l'Evaluation de la Consommation des Circuits Intégrés VLSI”, 1er Colloque CAO de Circuits Intégrés et Systèmes, Grenoble, France, pp. 116-119 [Dunoyer 1997d]
- J. Dunoyer, N. Abdallah, P. Bazargan Sabet : “Méthodes Probabilistes et Problèmes de Corrélations pour l'Evaluation de la Consommation des Circuits VLSI”, Journées Faible Tension Faible Consommation, Paris, France, pp. 131-134 [Dunoyer 1997e]
- P. Faudemay : “Segmentation multi-canaux de vidéos en séquences”, CORESA'97 - 3èmes journées d'études et d'échanges COmpression et REpresentation des Signaux Audiovisuels, Issy-Les-Moulineaux, France [Faudemay 1997a]
- P. Faudemay, C. Montacié, M.‑J. Caraty : “Video Indexing Based on Image and Sound”, International Conference on Multimedia Storage and Archivig System, vol. 3229, SPIE Proceedings, Dallas, TX, United States, pp. 57-69, (SPIE) [Faudemay 1997b]
- P. Faudemay, C. Seyrat : “Intelligent delivery of personalised video programmes from a video database”, 8th International Conference Database and ExpertSystems Applications (DEXA'97), Toulouse, France, pp. 172-177, (IEEE) [Faudemay 1997c]
- M. Firas, M. Marzouki, M. Touati : “A Cost-effective Approach for Analog, Digital and Mixed-signal Test and Diagnosis”, 2nd IEEE European Test Workshop, Cagliari, Italy [Firas 1997]
- O. Florent : “Génération distribuée de vecteurs de test par découpage structurel”, 1er Colloque CAO de Circuits Intégrés et Systèmes, Grenoble, France, pp. 242-245 [Florent 1997]
- A. Guyot, S.‑J. Abou‑Samra, M. Aberbour, A. Houelle, H. Mehrez, N. Vaucher : “Modelling and synthesis of optimal adders under left-to-right input arrival”, IFIP International Workshop on Logic and Architecture Synthesis (IWLAS'97), Grenoble, France, (IFIP) [Guyot 1997]
- D. Hommais, A. Greiner, F. Pétrot : “Un environnement de simulation pour les systèmes embarqués”, 1er Colloque CAO de Circuits Intégrés et Systèmes, Grenoble, France, pp. 66-69 [Hommais 1997]
- L. Jacomme, Rajesh K. Bawa : “Synthèse de descriptions comportementales séquentielles en conformité avec la sémantique VHDL”, 1er Colloque CAO de Circuits Intégrés et Systèmes, Grenoble, France, pp. 303-306 [Jacomme 1997]
- J.‑J. Lecler, A. Fenyö, A. Greiner, F. Potter : “SmartHSL : An Evaluation Board for the IEEE 1355 Technology.”, European Multimedia Microprocessor Systems and Electronic Commerce Conference and Exhibition (EMMSEC'97), Florence, Italy [Lecler 1997]
- A. Lester, A. Greiner, P. Bazargan Sabet : “Un Outil d'Evaluation de la Consommation Basée sur l'Extraction d'un Réseau de Portes Caractérisées”, 1er Colloque CAO de Circuits Intégrés et Systèmes, Grenoble, France, pp. 128-131 [Lester 1997]
- W. Maroufi, M. Marzouki : “Specification and Early Evaluation of System Testability through Object Oriented modeling”, 2nd IEEE European Test Workshop, Cagliari, Italy [Maroufi 1997]
- F. Mohamed, A. Khouas, A. Derieux : “L'optimisation des vecteurs de test analogique à base d'une approche floue”, Rencontre Francophone sur la Logique Floue et ses Applications (LFA'97), Lyon, France, pp. 107-112 [Mohamed 1997]
- O. Oliaei, H. Aboushady, P. Loumeau : “A Switched-Current Class AB Sigma-Delta-Modulator”, 30th IEEE International Symposium on Circuits and Systems (ISCAS'97), vol. 1, Hong Kong, Hong Kong, pp. 393-396, (IEEE) [Oliaei 1997a]
- O. Oliaei, H. Aboushady, P. Loumeau : “Simulation de Modulateurs Sigma-Delta à Courants Commutés”, 1er Colloque CAO de Circuits Intégrés et Systèmes, Grenoble, France, pp. 283-286 [Oliaei 1997b]
- F. Pétrot, D. Hommais, A. Greiner : “A Simulation Environment for Core Based Embedded Systems”, 30th Annual Simulation Symposium, Atlanta, Georgia, United States, pp. 86-91, (IEEE) [Pétrot 1997a]
- F. Pétrot, D. Hommais, A. Greiner : “Cycle Precise Core Based Hardware/Software System Simulation with Predictable Event Propagation”, 23rd Euromicro Conference, Budapest, Hungary, pp. 182-187, (IEEE) [Pétrot 1997b]
- E. Rejouan, H. Mehrez : “Automatic Generation Of Self Testing ROM”, 4th Mixed Design of Integrated Circuits and Systems (MIXDES'1997), Poznan, Poland, pp. 1-5 [Rejouan 1997]
- P. Remy, Ph. Royannez, A. Amara : “A GaAs electrical rule checker”, X Simposio Brasileiro de Concepcao de Circuitos Integrados (SBCCI '97), Gramado, Brazil, pp. 1-10 [Remy 1997]
- Ph. Royannez, A. Amara : “A CMOS/GaAs DCFL comparartive survey based upon custom designed multiplier generators”, First Electronic Circuits and Systeme Conference (ECS'97), Bratislava, Slovakia [Royannez 1997a]
- Ph. Royannez, A. Amara : “DCFL circuit buffering”, 7th international symposium on IC technology system & applications (ISIC'1997), Singapore, Singapore [Royannez 1997b]
- F. Wajsbürt, J.‑L. Desbarbieux, C. Spasevski, S. Penain, A. Greiner : “An Integrated PCI Component for IEEE 1355”, European Multimedia Microprocessor Systems and Electronic Commerce Conference and Exhibition (EMMSEC'97), Florence, Italy [Wajsbürt 1997a]
- F. Wajsbürt, K. Dioury, F. Pétrot : “Low Power, Process Independent, Full Transistor Controlled Slew Rate, PCI Compliant I/O pads”, 21st International Conference on Microelectronics, Nis, Serbia, pp. 811-814, (IEEE) [Wajsbürt 1997b]
- B. Zerrouk, A. Bouaraoua, F. Ilponse : “MILE : Experimental Study Of A Generic Router Under MILE”, IASTED Applied Informatic (IASTED AI'97), Innsbruck, Austria [Zerrouk 1997]