LIP6 1998/042
- Thesis
Analyse temporelle hiérarchique des circuits VLSI à très haute densité d'intégration - K. Dioury
- 194 pages - 10/26/1998- document en - http://www.lip6.fr/lip6/reports/1998/lip6.1998.042.ps.gz - 323 Ko
- Contact : Karim.Dioury (at) nulllip6.fr
- Ancien Thème : ASIM
- Keywords : Timing analysis, Hierarchical verification, Graph reduction
- Publisher : Francois.Dromard (at) nullasim.lip6.fr
Timing analysis is an important step in the verification of digital VLSI circuits. With the advent of deep submicronic technologies, static timing analysis has revealed itself as the only feasible method for the timing verification of circuits, which can nowadays reach up to several million transistors. Nevertheless, this method can generate an excessively large amount of data. To alleviate this problem, we have defined a method based on the hierarchical partitioning of the design phase. The propagation times within a circuit are represented using a multi-level hierarchical timing view. Propagation times of gates and RC networks are represented by a causality graph in which the nodes correspond to events on the signals, and the arcs correspond to the propagation times between two events on two signals. Each instance of the hierarchical tree is represented by a timing figure containing information relative to the causality graph which cannot be described in the timing figures associated with each sub-block instantiated by each of these instances. A method for the traversal of the causality graph has been defined, which limits the search for paths between connectors and registers to a small part of the graph. The approach also adopts a novel concept in timing analysis, that of critical path factorisation. This concept allows, thanks to its solution of the problem of quadratic growth in the number of paths, acceleration of the critical path search in a subsequently reduced causality graph. The multi-level timing view, which we have defined, has allowed us to produce the hierarchical timing analysis tool HITAS as well as the interactive path browser XTAS. Experimentation with these tools has shown that our approach can deal with circuits of extremely high integration density.