LIP6 1997/024
- Thesis
Etude d'un circuit de sérialisation a 3 Gbits/s en technologie BiCMOS - P. Couteaux
- 110 pages - 10/15/1997- document en - http://www.lip6.fr/lip6/reports/1997/lip6.1997.024.ps.gz - 6,039 Ko
- Contact : Pascal.Couteaux (at) nullst.com
- Ancien Thème : ASIM
- Keywords : Serial link, Delay Lock Loop, BiCMOS, Gigabit transmission, Bicmos Variable Delay
- Publisher : Francois.Dromard (at) nulllip6.fr
The microprocesseur speed need higher and higher data rates for data transmission. In order to solve this problem, serial links are more and more used. Effectively, they allow higher data rates for longer way than parallel links. Today, the fastest serial links on the market, designed in CMOS, Bipolar or AsGa,have data rates around 1 Giga bits per second. This thesis from the work realised by Roland Marbot team, into BULL society, on high speed and low consumption serial link macrocells. The maximum data rates of BULL HSL macrocell, in a 0.5 micron CMOS technology, is limited at 1 Giga bits per second. The goal of this thesis is to demonstrate we can already access higher data rates by translating the HSL comcepts into 0.5 Bicmos technologie. This document describes the new designs allowing to limit the contraints of the BiCMOS technology and to used its advantages. It also presents the results obtained ona BiCMOS serialiser chip in a 0.5 micron technology.