LIP6 2002/003
- Thesis
Étude et spécification d'un c.ur de processeur de traitement du signal configurable pour systèmes embarqués spécialisés - Y. Bajot
- 231 pages - 11/07/2001- document en - http://www.lip6.fr/lip6/reports/2002/lip6.2002.003.pdf - 9,803 Ko
- Contact : Yann.Bajot (at) nulllip6.fr
- Ancien Thème : ASIM
- Keywords : DSP processor, configurable model, VLIW architecture, generic instruction-set, design space exploration, retargetable compiler, instruction-set simulator, EFR vocoder, Viterbi algorithm, parameterizable macroblocks generator
- Publisher : Francois.Dromard (at) nulllip6.fr
The work presented here deals with the study and specification of a configurable DSP core model intended to be used in embedded systems. It also includes the definition of an associated design methodology which aims to speed up the design process of specialized DSP processors. We first present a detailed study of existing general/ specialized DSP processors. This study lead us to propose a DSP processor model based on a configurable VLIW architecture. It allows the user to adjust the number of general hardware resources and to include specialized custom units to improve performance of some critical applications. The control of the processor is managed by a generic, customizable, and variable length instruction-set. The design methodology include two phases. The first phase is called the design space exploration phase and consists to determine the best configuration for the processor model with regard to the application constraints. We present the instruction-set simulator and retargetable compiler used in this phase. The second phase deals with the hardware synthesis of the final configured processor. We propose an implementation method based on portable and parametrizable macroblocks generators. We apply the methodology to design a specialized DSP processor able to efficiently implement the GSM baseband functions. The analysis of the results in terms of performance and hardware cost clearly demonstrates the interest of a configurable processor model, which allows to obtain processors with best performance/cost ratio than those of general DSP processors.