DUPUIS Damien
Date de départ : 30/09/2011
Publications 2005-2011
Toutes
Communications
Posters
Thèse
2011
F. Javid, R. Iskander, M.‑M. Louërat, D. Dupuis : “Analog Circuits Sizing Using Bipartite Graphs ”, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Seoul, Korea, Republic of, pp. 1-4 (2011)
S. Youssef, D. Dupuis, R. Iskander, M.‑M. Louërat : “Routing Methodology For Nanometric Analog CMOS Devices ”, Colloque GDR SOC SIP, Lyon, France, pp. 1-2 (2011)
S. Youssef, D. Dupuis, R. Iskander, M.‑M. Louërat : “A Stack-Based Routing Methodology For Nanometric CMOS Devices ”, IEEE MOS-AK/GSA Workshop, Paris, France, pp. 1-2 (2011)
F. Javid, R. Iskander, M.‑M. Louërat, D. Dupuis : “Using Compact MOS Models for Hierarchical Sizing and Biasing of Analog IPs ”, IEEE MOS-AK/GSA Workshop, Paris, France, pp. 1-2 (2011)
S. Youssef, F. Javid, D. Dupuis, R. Iskander, M.‑M. Louërat : “A Python-Based Layout-Aware Analog Design Methodology For Nanometric Technologies ”, IEEE 6th International Design and Test Workshop (IDT), Beyrouth, Lebanon, pp. 62-67 (2011)
S. Youssef, D. Dupuis, R. Iskander, M.‑M. Louërat : “A Stack-Based Routing Methodology For Nanometric Analogue CMOS Devices ”, The IEEE Virtual Worldwide Forum For PhD Researchers in Electronic Design Automation, (VW FEDA), Southampton, United Kingdom, pp. 1-6 (2011)
S. Youssef, F. Javid, D. Dupuis, R. Iskander, M.‑M. Louërat : “A Seamless Representation for Coupling Transistor Sizing with Nanometric CMOS Layout Generation ”, 20th European Conference on Circuit Theory and Design (ECCTD), Linkoping, Sweden, pp. 341-344 (2011)
2010
S. Youssef, D. Dupuis, R. Iskander, M.‑M. Louërat : “A Python-Based Analog Layout Generation Tool For Nanometer CMOS Technologies ”, Colloque national du GDR SOC-SIP, Cergy, France, pp. 1-2 (2010)
F. Javid, R. Iskander, M.‑M. Louërat, D. Dupuis : “A Design Environment for Analog IPs Design Knowledge Capture and Migration ”, Colloque GDR SOC-SIP : System-On-Chip, System-In-Package, Paris, France, pp. 1-2 (2010)
S. Youssef, D. Dupuis, R. Iskander, M.‑M. Louërat : “Automatic Stress Effects Computation Based On A Layout Generation Tool For Analog IC ”, 2010 IEEE International Behavioral Modeling and Simulation Conference (BMAS 2010), San Jose, CA, United States, pp. 7-12 (2010)
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