Direction de recherche : Meryem MARZOUKI
Conception en vue du test de systèmes intégrés sur silicium (SoC)
Soutenance : 27/09/2002Membres du jury :
Christian Landrault - rapporteur
Paolo Prinetto - rapporteur
Laroussi Bouzaida
Alain Greiner
Mereym Marzoukli Date de départ : 01/10/2003
Publications 2000-2014
Toutes
Articles de revues
Communications
Soutenance de thèse
2014
S.‑U. Rehman, A. Blanchardon, A. Ben Dhia, M. Benabdenbi, R. Chotin‑Avot, L. Naviner, L. Anghel, H. Mehrez, E. Amouri, Z. Marrakchi : “Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA ”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI'14), Tampa, FL, United States, pp. 553-558, (IEEE) (2014)
Zh. Zhang, D. Refauvelet, A. Greiner, M. Benabdenbi, F. Pêcheux : “On-the-Field Test and Configuration Infrastructure for 2-D-Mesh NoCs in Shared-Memory Many-Core Architectures ”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22 (6), pp. 1364-1376, (IEEE) (2014)
2013
A. Ben Dhia, S. Ur Rehman, A. Blanchardon, L. Naviner, M. Benabdenbi, R. Chotin‑Avot, H. Mehrez, E. Amouri, Z. Marrakchi : “A Defect-tolerant Cluster in a Mesh SRAM-based FPGA ”, International Conference on Field-Programmable Technology (FPT), Kyoto, Japan, pp. 434-437, (IEEE Computer Society) (2013)
2011
2010
E. Faure, M. Benabdenbi, F. Pêcheux : “Distributed online software monitoring of manycore architectures ”, 16th IEEE International On-Line Testing Symposium, Corfou Island, Greece, pp. 56-61, (IEEE) (2010)
Zh. Zhang, A. Greiner, M. Benabdenbi : “Fully Distributed Initialization Procedure for a 2D-Mesh NoC, Including Off Line BIST and Partial Deactivation of Faulty Components ”, The 16th IEEE International On-Line Testing Symposium (IOLTS), Corfu, Greece, pp. 194-196 (2010)
E. Faure, G. Marchesan Almeida, M. Benabdenbi, P. Benoit, F. Clermidy, F. Pêcheux, G. Sassatelli, L. Torres : “An In-Memory Monitoring Database For Self Adaptive MP²SoCs ”, IEEE International Conference on Design and Architectures for Signal and Image Processing, Edimbourg, United Kingdom, pp. 97-104 (2010)
2009
2007
M. Tuna, M. Benabdenbi, A. Greiner : “At-Speed Testing of Core-Based System-On-Chip Using an Embedded Micro-Tester ”, VTS IEEE VLSI Test Symposium, Berkeley, California, United States, pp. 447-454, (IEEE) (2007)
M. Tuna, O. Garcia, M. Benabdenbi : “Software-Based Self-Test Strategies for Memory Caches of RISC Processor Cores ”, LATW IEEE Latin-American Test Workshop, Cuzco, Peru, pp. 124-130 (2007)
2006
A. Greiner, F. Pétrot, M. Carrier, M. Benabdenbi, R. Chotin‑Avot, R. Labayrade : “MP-SoC Architecture for an Obstacle Detection Application in Pre-Crash Situation ”, 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'06), Montpellier, France, pp. 24-30, (Université Montpellier II) (2006)
M. Tuna, M. Benabdenbi, A. Greiner : “T-Proc: An Embedded IEEE1500-Wrapped Cores Tester ”, PRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics, Otranto, Italy, pp. 493-496, (IEEE) (2006)
M. Tuna, M. Benabdenbi, A. Greiner : “STESOC: A Software-Based Test-Access-Mechanism Controller ”, ETS IEEE European Test Symposium, Southampton, United Kingdom, pp. 91-96 (2006)
M. Tuna, M. Benabdenbi : “Software-Based Self-Test of Register Files in RISC Processor Cores using March Algorithms ”, LATW IEEE Latin-American Test Workshop digest of papers, Buenos Aires, Argentina, pp. 67-72 (2006)
A. Greiner, F. Pétrot, M. Carrier, M. Benabdenbi, R. Chotin‑Avot, R. Labayrade : “Mapping an obstacles detection, stereo vision-based, software application on a multi-processor system-on-chip ”, IV 2006 - IEEE Intelligent Vehicles Symposium, Tokyo, Japan, pp. 370-376, (IEEE) (2006)
2005
M. Tuna, M. Benabdenbi, A. Greiner : “STESI: a new software-based strategy for testing socs containing wrapped IP cores ”, MIXDES 2005 - 12th International conference on Mixed Design of Integrated Circuits and Systems, Krakow, Poland, pp. 459-464 (2005)
M. Tuna, M. Benabdenbi, A. Greiner : “STESI: Testing wrapped IP cores using a dedicated Test Processor ”, I-IP IEEE International Workshop on Infrastructure IP, Palm Springs, California, United States, pp. 60-66 (2005)
2004
2002
2001
2000
W. Maroufi, M. Benabdenbi, M. Marzouki : “Solving the I/O Bandwidth Problem in System on a Chip Testing ”, XIII Symposium on Integrated Circuits and Systems Design (SBCCI'00), Manaus, Brazil, pp. 9-14, (IEEE) (2000)
W. Maroufi, M. Benabdenbi, M. Marzouki : “Controlling the CAS-BUS TAM with IEEE 1149.1 TAP: A Solution for Systems-On-a-Chip Testing ”, 4th IEEE International Workshop on Testing Embedded Core-based Systems (TECS'00), Montréal, Canada (2000)
M. Benabdenbi, W. Maroufi, M. Marzouki : “CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip ”, Design Automation and Test in Europe Conference (DATE'2000), Paris, France, pp. 141-145, (IEEE) (2000)