2005-2011 Publications

• 2011
  • F. Javid, R. Iskander, M.‑M. Louërat, D. Dupuis : “Analog Circuits Sizing Using Bipartite Graphs”, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Seoul, Korea, Republic of, pp. 1-4 (2011)
  • S. Youssef, D. Dupuis, R. Iskander, M.‑M. Louërat : “Routing Methodology For Nanometric Analog CMOS Devices”, Colloque GDR SOC SIP, Lyon, France, pp. 1-2 (2011)
  • S. Youssef, D. Dupuis, R. Iskander, M.‑M. Louërat : “A Stack-Based Routing Methodology For Nanometric CMOS Devices”, IEEE MOS-AK/GSA Workshop, Paris, France, pp. 1-2 (2011)
  • F. Javid, R. Iskander, M.‑M. Louërat, D. Dupuis : “Using Compact MOS Models for Hierarchical Sizing and Biasing of Analog IPs”, IEEE MOS-AK/GSA Workshop, Paris, France, pp. 1-2 (2011)
  • S. Youssef, F. Javid, D. Dupuis, R. Iskander, M.‑M. Louërat : “A Python-Based Layout-Aware Analog Design Methodology For Nanometric Technologies”, IEEE 6^th International Design and Test Workshop (IDT), Beyrouth, Lebanon, pp. 62-67 (2011)
  • S. Youssef, D. Dupuis, R. Iskander, M.‑M. Louërat : “A Stack-Based Routing Methodology For Nanometric Analogue CMOS Devices”, The IEEE Virtual Worldwide Forum For PhD Researchers in Electronic Design Automation, (VW FEDA), Southampton, United Kingdom, pp. 1-6 (2011)
  • S. Youssef, F. Javid, D. Dupuis, R. Iskander, M.‑M. Louërat : “A Seamless Representation for Coupling Transistor Sizing with Nanometric CMOS Layout Generation”, 20^th European Conference on Circuit Theory and Design (ECCTD), Linkoping, Sweden, pp. 341-344 (2011)
• 2010
  • S. Youssef, D. Dupuis, R. Iskander, M.‑M. Louërat : “A Python-Based Analog Layout Generation Tool For Nanometer CMOS Technologies”, Colloque national du GDR SOC-SIP, Cergy, France, pp. 1-2 (2010)
  • F. Javid, R. Iskander, M.‑M. Louërat, D. Dupuis : “A Design Environment for Analog IPs Design Knowledge Capture and Migration”, Colloque GDR SOC-SIP : System-On-Chip, System-In-Package, Paris, France, pp. 1-2 (2010)
  • S. Youssef, D. Dupuis, R. Iskander, M.‑M. Louërat : “Automatic Stress Effects Computation Based On A Layout Generation Tool For Analog IC”, 2010 IEEE International Behavioral Modeling and Simulation Conference (BMAS 2010), San Jose, CA, United States, pp. 7-12 (2010)
• 2009
  • D. Dupuis : “Routeur Global pour la plateforme Coriolis”, thesis, phd defence 06/17/2009, supervision Munier, Alix, co-supervision : Masson, Christian (2009)
• 2007
  • S. Belloeil, D. Dupuis, Ch. Masson, J.‑P. Chaput, H. Mehrez : “Stratus: A procedural circuit description language based upon Python”, ICM International Conference on Microelectronics, Cairo, Egypt, pp. 275-278, (IEEE) (2007)
• 2005
  • D. Dupuis : “Etude comparative de deux algorithmes de placement de systèmes intégrés sur puce”, JNRDM 2005 - Journées Nationales du Réseau Doctoral en Microélectronique, Paris, France, pp. 55-57 (2005)