Supervision : Emmanuel CHAILLOUX

Co-supervision : SEROT Jocelyn (CNRS/UCA/SIGMA)

Safe, expressive and efficient FPGA programming

FPGAs (Field-Programmable Gate Arrays) are reconfigurable digital circuits: their behavior can be customized by logic synthesis of specification at the so-called register transfer level (RT level), in hardware description languages such as VHDL or Verilog.
FPGAs are well suited to implement reactive systems, directly as synchronous circuits interacting with the external environment via I/O pins – the logic synthesizer ensuring that timing constraints are met, given the FPGA clock frequency.
FPGAs are also used to implement hardware accelerators ; however, RT-level descriptions of transformational systems (or “computations”) – with latencies of several clock cycles – are difficult to debug, maintain and manually optimize. High-Level Synthesis (HLS) offers a simpler way of expressing computations, using a programming language compiled at the RT level. The advantage of this approach is to keep the implementation details hidden from the programmer, leaving the compiler responsible for scheduling computations over time. However, this leads to a loss of control over temporal behavior and therefore safety and efficiency for the circuits generated. As embedded systems, especially those based on FPGAs, need to perform more and more computations, while interacting with their environment, this thesis proposes a programming model to combine hardware description (data-flow oriented) and general-purpose parallel computation (control-flow oriented) using a synchronous approach. This programming model forms the basis for the design and implementation of Eclat, a functional-imperative, parallel and synchronous programming language, compiled to VHDL. Eclat is sufficiently precise to describe synchronous circuits at the RT level. It facilitates the programming of hardware accelerators, with a clear and predictable temporal semantics by which to exploit time-space trade-offs. Any Eclat program is reactive, with a mechanism for embedding computations within programs and thereby mix computation and interaction. Eclat also offers shared memory (in the form of RAM blocks), with deterministic concurrency. It is used to develop programming abstractions such as algorithmic skeletons and virtual machine implementations for high-level languages. This address, at various levels, the need to run general-purpose algorithms within FPGA-based reactive embedded applications.

2020-2024 Publications

• 2024
  • L. Sylvestre, J. Sérot, E. Chailloux : “Programming parallelism on FPGAs with Eclat”, Proceedings of 17^th International Symposia on High-Level Parallel Programming and Applications HLPP 2024, Proceedings of 17^th INTERNATIONAL SYMPOSIUM ON HIGH-LEVEL PARALLEL PROGRAMMING AND APPLICATIONS HLPP 2024, Pisa, Italy, pp. pp.69-88 (2024)
  • L. Sylvestre, E. Chailloux, J. Sérot : “Work-in-Progress: mixing computation and interaction on FPGA”, Proceedings of the International Conference on Embedded Software, Hambourg, Germany, pp. pp.5-6, (ACM), (ISBN: 9798400702914) (2024)
  • L. Sylvestre, J. Sérot, E. Chailloux : “Hardware Implementation of OCaml Using a Synchronous Functional Language”, Practical Aspects of Declarative Languages, vol. 14512, Lecture Notes in Computer Science, Londres, United Kingdom, pp. 151-168, (Springer Nature Switzerland), (ISBN: 978-3-031-52037-2) (2024)
• 2023
  • L. Sylvestre, E. Chailloux, J. Sérot : “Accelerating OCaml Programs on FPGA”, International Journal of Parallel Programming, vol. 51 (Special Issue on High-Level Parallel Programming and Applications (HLPP 2022)), pp. 186–207, (Springer Verlag) (2023)
• 2022
  • L. Sylvestre, E. Chailloux, J. Sérot : “Accelerating OCaml programs on FPGA”, 15^th International Symposium on High-level Parallel Programming and Applications (HLPP 2022), Porto, Portugal (2022)
  • L. Sylvestre, J. Sérot, E. Chailloux : “A Virtual Machine Approach for High-level FPGA Programming”, 2022 IEEE 30^th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), New York City, United States, (IEEE) (2022)
  • L. Sylvestre, J. Sérot, E. Chailloux : “Macle : un langage dédié à l’accélération de programmes OCaml sur circuits FPGA”, Journées Francophones des Langages Applicatifs, Saint-Médard-d'Excideuil, France, pp. 93-109 (2022)
• 2020
  • L. Sylvestre, E. Chailloux : “Expérimentations pédagogiques en Learn-OCaml”, 31^e Journées Francophones des Langages Applicatifs, Gruissan, France (2020)