Supervision : Gilles MULLER

Co-supervision : GRACIA PÉREZ Daniel, SOPENA Julien

Characterization of the sensitivity to memory interferences in real-time systems embedded on multi-core platforms

Interference on the memory system can cause significant slowdowns to applications running in parallel on COTS multi-core processors. They are caused by concurrent accesses to shared hardware resources in the memory system. The magnitude of the delays caused by this phenomenon is difficult to predict, making interference a major obstacle to the adoption of COTS multi-core processors in real-time systems.
This thesis is devoted to the characterization of the sensitivity of an application to memory interferences based on a characterization of its behavior in isolation. The goal is to determine a priori if an application is sensitive to this problem or not. Using a set of microbenchmarks that we have previously introduced, we show that a purely quantitative characterization of memory access behavior characterizes the sensitivity to interference in a very imprecise way.
In order to allow a more precise characterization of sensitivity, we introduce different metrics to quantify quantitative and qualitative aspects of memory use. In order to measure these metrics, we implement a profiler prototype based on dynamic binary instrumentation approaches.
In addition to allowing the measurement of qualitative aspects, this tool produces high-resolution profiles that clearly distinguish the different phases in application behaviors. Finally, we use data from our microbenchmarks to train a machine learning algorithm according to several characterizations.
Experimental results show significant reductions in error reduction for the prediction of the delay undergone by applications of the MiBench and PARSEC suites.

2016-2020 Publications

• 2020
  • C. Courtaud : “Caractérisation de la sensibilité aux interférences mémoire dans les systèmes temps-réels embarqués sur des plateformes multi-coeurs”, thesis, phd defence 01/28/2020, supervision Muller, Gilles, co-supervision : Gracia, PÉREZ Daniel, Sopena, Julien (2020)
• 2019
  • C. Courtaud, J. Sopena, G. Muller, D. Gracia : “Improving Prediction Accuracy of Memory Interferences for Multicore Platforms”, RTSS 2019 - 40^th IEEE Real-Time Systems Symposium, Hong-Kong, China, (IEEE) (2019)
• 2016
  • A. Blin, C. Courtaud, J. Sopena, J. Lawall, G. Muller : “Maximizing Parallelism without Exploding Deadlines in a Mixed Criticality Embedded System”, 28^th EUROMICRO Conference on Real-Time Systems (ECRTS'16), Toulouse, France (2016)
  • A. Blin, C. Courtaud, J. Sopena, J. Lawall, G. Muller : “Understanding the Memory Consumption of the MiBench Embedded Benchmark”, Netys, Marakech, Morocco (2016)
  • A. Blin, C. Courtaud, J. Sopena, J. Lawall, G. Muller : “Maximizing Parallelism without Exploding Deadlines in a Mixed Criticality Embedded System”, (2016)