BLIN Antoine
Supervision : Gilles MULLER
Co-supervision : SOPENA Julien
Towards an efficient use of multi-core processors in mixed criticality embedded systems
Complex embedded systems today commonly involve a mix of real-time and best-effort applications integrated on separate microcontrollers thus ensuring fault isolation and error containment. However, this solution multiplies hardware costs, power consumption and thermal dissipation.
The recent emergence of low-cost multi-core processors raises the possibility of running both kinds of applications on a single machine, with virtualization ensuring isolation. Nevertheless, the memory hierarchy on such processors is shared between all cores. Memory accesses done by a real time application running on one dedicated core can be slowed down by concurrent memory accesses initiated by best effort applications running in parallels. Therefore real time applications can miss their deadlines.
In this thesis, we propose a run-time software-regulation approach that aims to maximize parallelism between real-time and best-effort applications running on a single low-cost multicore ECU. Our approach uses an overhead estimation derived from offline profiling of the real-time application to estimate the slow down on the real-time application caused by memory interferences. When the estimated overhead reaches a predefined threshold, our approach suspends the best-effort applications, allowing the real-time task to continue executing without interferences. Suspended best-effort applications are resumed when the real-time application ends its current activation.
Defence : 01/30/2017
Jury members :
Mme Claire Pagetti, Ingénieur de recherche-HDR, ONERA [Rapporteur]
Mme Isabelle Puaut, Directrice de recherche, Inria [Rapporteur]
Mme Béatrice Bérard, Professeur, Université Pierre et Marie Curie
M. Marc Gatti, Directeur recherche & technologie, Thales
Mme Sophie Quinton, Chargés de recherche, Inria
M. Gilles Muller, Directeur de recherche, Inria
M. Julien Sopena, Maître de conférences, Université Pierre et Marie Curie
2014-2023 Publications
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2023
- E. Louet, A. Blin, J. Sopena, Ah. Amamou, K. Haddadou : “Effects of secured DNS transport on resolver performance”, IEEE Symposium on Computers and Communications (ISCC), Gammarth, Tunisia, pp. 238-244, (IEEE), (ISBN: 979-8-3503-0048-2) (2023)
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2021
- Y. Ghigoff, J. Sopena, K. Lazri, A. Blin, G. Muller : “BMC: Accelerating Memcached using Safe In-kernel Caching and Pre-stack Processing”, NSDI'21 - 18th USENIX Symposium on Networked Systems Design and Implementation, Virtual event, United States, pp. 487-501, (USENIX Association) (2021)
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2017
- A. Blin : “Vers une utilisation efficace des processeurs multi-cœurs dans des systèmes embarqués à criticités multiples”, thesis, phd defence 01/30/2017, supervision Muller, Gilles, co-supervision : Sopena, Julien (2017)
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2016
- A. Blin, C. Courtaud, J. Sopena, J. Lawall, G. Muller : “Maximizing Parallelism without Exploding Deadlines in a Mixed Criticality Embedded System”, 28th EUROMICRO Conference on Real-Time Systems (ECRTS'16), Toulouse, France (2016)
- A. Blin, C. Courtaud, J. Sopena, J. Lawall, G. Muller : “Understanding the Memory Consumption of the MiBench Embedded Benchmark”, Netys, Marakech, Morocco (2016)
- A. Blin, C. Courtaud, J. Sopena, J. Lawall, G. Muller : “Maximizing Parallelism without Exploding Deadlines in a Mixed Criticality Embedded System”, (2016)
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2014
- A. Blin, J. Sopena, G. Muller, Y. Laarouchi : “Contrôle de la bande passante mémoire dans les systèmes à criticité mixte par sous-réservation”, ComPAS 2014 - Conférence d'informatique en Parallélisme, Architecture et Systeme, Neuchâtel, Switzerland (2014)