Supervision : Alain GREINER

Co-supervision : WAJSBÜRT Franck

Protocoles scalables de cohérence des caches pour processeurs manycore à espace d'adressage partagé visant la basse consommation

The TSAR architecture (Tera-Scale ARchitecture) developed jointly by Lip6 Bull and CEA-LETI is a CC-NUMA manycore architecture which is scalable up to 1024 cores. The DHCCP cache coherence protocol in the TSAR architecture is a global directory protocol using the write-through policy in the L1 cache for scalability purpose, but this write policy causes a high power consumption which we want to reduce. Currently the biggest semiconductors companies, such as Intel or AMD, use the MESI MOESI protocols in their multi-core processors. These protocols use the write-back policy to reduce the high power consumption due to writes. However, the complexity of implementation and the sharp increase in the coherencet traffic when the number of processors increases limits the scalability of these protocols beyond a few dozen cores.
In this thesis, we propose a new cache coherence protocol using a hybrid method to process write requests in the L1 private cache : for exclusive lines, the L1 cache controller chooses the write-back policy in order to modify locally the lines as well as eliminate the write traffic for exclusive lines. For shared lines, the L1 cache controller uses the write-through policy to simplify the protocol and in order to guarantee the scalability.
We also optimized the current solution for the TLB coherence problem in the TSAR architecture. The new method which is called CC-TLB not only improves the performance, but also reduces the energy consumption.
Finally, this thesis introduces a new micro cache between the core and the L1 cache, which allows to reduce the number of accesses to the instruction cache, in order to save energy without any impact on performances.

2015-2017 Publications

• 2017
  • H. Liu, Quentin L. Meunier, A. Greiner : “Decoupling Translation Lookaside Buffer Coherence from Cache Coherence”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2017), Bochum, Germany, pp. 92-97, (IEEE) (2017)
• 2016
  • H. Liu : “Protocoles scalables de cohérence des caches pour processeurs manycore à espace d’adressage partagé visant la basse consommation”, thesis, phd defence 01/27/2016, supervision Greiner, Alain, co-supervision : Wajsbürt, Franck (2016)
• 2015
  • H. Liu, C. Dévigne, L. Garcia, Quentin L. Meunier, F. Wajsbürt, A. Greiner : “RWT: Suppressing Write-Through Cost When Coherence is Not Needed”, Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, Montpellier, France, pp. 434-439, (IEEE) (2015)