Supervision : Habib MEHREZ

Co-supervision : MARRAKCHI Zied

High Performance Three-Dimensional Tree-based FPGA Architecture using 3D Technology Process

Today, FPGAs (Field Programmable Gate Arrays) has become important actors in the computational devices domain that was originally dominated by microprocessors and ASICs. FPGA design big challenge is to need a good trade-off between flexibility and performances. Three factors are combined to determine the characteristics of an FPGA: quality of its architecture, quality of the CAD tools used to map circuits into the FPGA, and its electrical technology design. This dissertation aims at exploring a development of Three- dimensional (3D) physical design methodology and exploration tools for 3D Tree-based stacked FPGA architecture to improve area, density, power and performances.
The first part of the dissertation is to study the existing variants of 2D Tree-based FPGA architecture and the impact of 3D migration on its topology. We have seen numerous studies showing the characteristics of Tree-based interconnect networks, how they scale in terms of area and performance, and empirically how they relate to particular designs. Nevertheless we never had any breakthrough in optimizing these network topologies to exploit the advantages in area and power consumption and how to deal with the larger wire-length issues that impede performance of Tree-based FPGA architecture. Through the course of the work, we understand that, we would not be able to optimize the speed, unless we break the very backbone of the Tree-based interconnect network and resurrect again by using 3D technology. The 3D-ICs can alleviate interconnect delay issues by ofering exibility in system design, placement and routing. A new set of 3D FPGA architecture exploration tools and technologies developed to validate the advance in performance and area.
The second contribution of this thesis is the development 3D physical design methodology and tools using existing 2D CAD tools for the implementation of 3D Tree-based FPGA demonstrator. During the course of design process, we addressed many specic issues that 3D designers will encounter dealing with tools that are not specically designed to meet their needs. In contrast, the thermal performance is expected to worsen with the use of 3D integration. We examined precisely how thermal behavior scales in 3D integration and determine how the temperature can be controlled using thermal design techniques.

2013-2016 Publications

• 2016
  • S. Chtourou, Z. Marrakchi, E. Amouri, V. Pangracious, M. Abid, H. Mehrez : “Improvement of cluster-based Mesh FPGA architecture using novel hierarchical interconnect topology and long routing wires”, Microprocessors and Microsystems: Embedded Hardware Design, vol. 40, pp. 16-26, (Elsevier) (2016)
  • S. Chtourou, Z. Marrakchi, E. Amouri, V. Pangracious, H. Mehrez, M. Abid : “Exploration of Mesh-Based FPGA Architecture: Comparison of 2D and 3D Technologies in Terms of Power, Area and Performance”, PDP 2016 - 24^th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, Heraklion, Crete, Greece, pp. 635-642, (IEEE Computer Society) (2016)
• 2015
  • S. Chtourou, Z. Marrakchi, V. Pangracious, E. Amouri, H. Mehrez, M. Abid : “Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization”, ARC 2015 - 11^th International Symposium on Applied Reconfigurable Computing, vol. 9040, Lecture Notes in Computer Science, Bochum, Germany, pp. 411-418, (Springer) (2015)
  • V. Pangracious, Z. Marrakchi, H. Mehrez : “Design and Optimization of a Horizontally Partitioned, High-Speed, 3D Tree-Based FPGA”, IEEE Micro, vol. 35 (6), pp. 48-59, (Institute of Electrical and Electronics Engineers) (2015)
  • V. Pangracious, Z. Marrakchi, H. Mehrez : “Three-Dimensional Design Methodologies for Tree-based FPGA Architecture”, vol. 350, Lecture Notes in Electrical Engineering, (Springer), (ISBN: 978-3-319-19173-7) (2015)
• 2014
  • V. Pangracious : “Haute Performance tridimensionnelle a base de FPGA Arborescents Architecture a l’aide de la technologie 3D processus”, thesis, phd defence 11/24/2014, supervision Mehrez, Habib, co-supervision : Marrakchi, Zied (2014)
  • V. Pangracious, E. Amouri, Z. Marrakchi, H. Mehrez : “Architecture level optimization of 3-dimensional tree-based FPGA”, Microelectronics Journal, vol. 45 (4), pp. 355-366, (Elsevier) (2014)
  • S. Chtourou, M. Abid, V. Pangracious, E. Amouri, Z. Marrakchi, H. Mehrez : “Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation”, 3DIC 2014 - 2014 International 3D Systems Integration Conference, Kinsdale, Ireland, pp. 1-7, (IEEE) (2014)
  • V. Pangracious, M. Marrakchi, H. Mehrez, Z. Marrakchi : “On wiring delays reduction of tree-based FPGA using 3-D fabric”, SOCC 2014 - 27^th IEEE International System-on-Chip Conference, Las Vegas, NV, United States, pp. 64-69, (IEEE) (2014)
  • V. Pangracious, Z. Marrakchi, N. Beltaief, H. Mehrez, U. Farooq : “Exploration and optimization of heterogeneous interconnect fabric of 3D tree-based FPGA”, DTIS 2014 - 9^th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, Santorini, Greece, pp. 1-6, (IEEE) (2014)
• 2013
  • V. Pangracious, H. Mehrez, Z. Marrakchi : “Designing a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technology”, IEEE International 3D Systems Integration Conference (3DIC), 2013, San Francisco, CA, United States, pp. 1-8, (IEEE) (2013)
  • V. Pangracious, H. Mehrez, U. Farooq, Z. Marrakchi : “High Performance 3-Dimensional Heterogeneous Tree-based FPGA Architectures (HT-FPGA)”, FPGAworld'13 - The 10^th FPGAworld Conference, Stockholm, Sweden, pp. 3:1-3:6, (ACM) (2013)
  • V. Pangracious, H. Mehrez, Z. Marrakchi : “Designing 3D tree-based FPGA: Interconnect Optimization and Thermal Analysis”, NEWCAS'13 - IEEE 11^th International Conference on New Circuits and Systems, Paris, France, pp. 1-4, (IEEE) (2013)
  • V. Pangracious, E. Amouri, H. Mehrez, Z. Marrakchi : “Physical Design Exploration of 3D Tree-based FPGA Architecture”, GLSVLSI'13 - The 23^rd ACM international conference on Great lakes symposium on VLSI, Paris, France, pp. 335-336, (ACM) (2013)
  • V. Pangracious, H. Mehrez, Z. Marrakchi : “Architecture Level TSV Count Minimization Methodology for 3D Tree-based FPGA”, Cool Chips XVI, Yokohama, Japan, pp. 1-3, (IEEE) (2013)
  • V. Pangracious, Z. Marrakchi, E. Amouri, H. Mehrez : “Performance analysis and optimization of high density tree-based 3d multilevel FPGA”, Reconfigurable Computing: Architectures, Tools and Applications, vol. 7806, Lecture Notes in Computer Science, Los Angeles, CA, United States, pp. 197-209, (Springer) (2013)
  • V. Pangracious, Z. Marrakchi, H. Mehrez : “Design and optimization of heterogeneous tree-based FPGA using 3D technology”, FPT 2013 - International Conference on Field-Programmable Technology, Kyoto, Japan, pp. 334-337, (IEEE) (2013)
  • V. Pangracious, H. Mehrez, N. Beltaief, Z. Marrakchi, U. Farooq : “Exploration environment for 3D heterogeneous tree-based FPGA architectures (3D HT-FPGA)”, ReConFig 2013 - International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, pp. 1-6, (IEEE) (2013)
  • V. Pangracious, H. Mehrez, Z. Marrakchi : “TSV count minimization and thermal analysis for 3D Tree-based FPGA”, ICICDT 2013 - International Conference on IC Design & Technology, Pavia, Italy, pp. 223-226, (IEEE) (2013)