Supervision : Alain GREINER

Transaction level modeling with distributed time and released synchronization techniques in order to parallely simulate many-core architectures

TLM-DT modeling techniques, based on the highest abstraction level of the SystemC hardware description language (SystemC TLM), are a first step to the parallel simulation of many-core architecture processors modeled at transactional level. TLM-DT modeling techniques made possible to simulate efficiently and accurately some architectures containing a large number of initiators and targets connected by a single interconnects network.
The goal of this thesis is on one hand to demonstrate the feasibility of the transactional modeling of a many-core architecture containing multiple cache levels and several interconnect networks and on the other hand to evolve TLM-DT modeling techniques in order to make them even more efficient for parallel simulations while maintaining the accurary guarantees. The many-core architecture used as a basis for this study is the TSAR architecture.
We demonstrate that the modeling and the performance evaluation of a shared memory many-core architecture containing several interconnects networks is feasible using a released synchronisation protocol which allows phase shifting between components. Using a released synchronization protocol (TLMDT-R) also provides a nearly linear speedup up to 32 processors of simulation, while using a strict synchronisation protocol (TLM-DT) provides a nearly linear speedup up to 8 processors of simulation. Using a released synchronisation protocol may however have significant consequences on the accuracy if the release of synchronization is too big.

2013 Publications

• 2013
  • H. Gioja : “Techniques de modélisation transactionnelle en temps distribué avec synchronisation relâchée pour la simulation parallèle d’architectures many-core”, thesis, phd defence 12/16/2013, supervision Greiner, Alain (2013)